2 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <mach/ddrphy-regs.h>
11 /* Select either decimal or hexadecimal */
13 #define PRINTF_FORMAT "%2d"
15 #define PRINTF_FORMAT "%02x"
20 static u32 read_bdl(struct ddrphy_datx8 __iomem *dx, int index)
22 return (readl(&dx->bdlr[index / 5]) >> (index % 5 * 6)) & 0x3f;
25 static void dump_loop(void (*callback)(struct ddrphy_datx8 __iomem *))
28 struct ddrphy __iomem *phy;
30 for (ch = 0; ch < NR_DDRCH; ch++) {
31 for (p = 0; p < NR_DDRPHY_PER_CH; p++) {
32 phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p);
34 for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
35 printf("CH%dP%dDX%d:", ch, p, dx);
36 (*callback)(&phy->dx[dx]);
43 static void __wbdl_dump(struct ddrphy_datx8 __iomem *dx)
47 for (i = 0; i < 10; i++)
48 printf(FS PRINTF_FORMAT, read_bdl(dx, i));
50 printf(FS "(+" PRINTF_FORMAT ")", readl(&dx->lcdlr[1]) & 0xff);
55 printf("\n--- Write Bit Delay Line ---\n");
56 printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
58 dump_loop(&__wbdl_dump);
61 static void __rbdl_dump(struct ddrphy_datx8 __iomem *dx)
65 for (i = 15; i < 24; i++)
66 printf(FS PRINTF_FORMAT, read_bdl(dx, i));
68 printf(FS "(+" PRINTF_FORMAT ")", (readl(&dx->lcdlr[1]) >> 8) & 0xff);
73 printf("\n--- Read Bit Delay Line ---\n");
74 printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
76 dump_loop(&__rbdl_dump);
79 static void __wld_dump(struct ddrphy_datx8 __iomem *dx)
82 u32 lcdlr0 = readl(&dx->lcdlr[0]);
83 u32 gtr = readl(&dx->gtr);
85 for (rank = 0; rank < 4; rank++) {
86 u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
87 u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
89 printf(FS PRINTF_FORMAT "%sT", wld,
90 wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
96 printf("\n--- Write Leveling Delay ---\n");
97 printf(" Rank0 Rank1 Rank2 Rank3\n");
99 dump_loop(&__wld_dump);
102 static void __dqsgd_dump(struct ddrphy_datx8 __iomem *dx)
105 u32 lcdlr2 = readl(&dx->lcdlr[2]);
106 u32 gtr = readl(&dx->gtr);
108 for (rank = 0; rank < 4; rank++) {
109 u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
110 u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
112 printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
116 void dqsgd_dump(void)
118 printf("\n--- DQS Gating Delay ---\n");
119 printf(" Rank0 Rank1 Rank2 Rank3\n");
121 dump_loop(&__dqsgd_dump);
124 static void __mdl_dump(struct ddrphy_datx8 __iomem *dx)
127 u32 mdl = readl(&dx->mdlr);
128 for (i = 0; i < 3; i++)
129 printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
134 printf("\n--- Master Delay Line ---\n");
135 printf(" IPRD TPRD MDLD\n");
137 dump_loop(&__mdl_dump);
140 #define REG_DUMP(x) \
141 { u32 __iomem *p = &phy->x; printf("%3d: %-10s: %p : %08x\n", \
142 p - (u32 *)phy, #x, p, readl(p)); }
147 struct ddrphy __iomem *phy;
149 printf("\n--- DDR PHY registers ---\n");
151 for (ch = 0; ch < NR_DDRCH; ch++) {
152 for (p = 0; p < NR_DDRPHY_PER_CH; p++) {
153 printf("== Ch%d, PHY%d ==\n", ch, p);
154 printf(" No: Name : Address : Data\n");
156 phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p);
190 static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
197 if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
200 if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
203 if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
206 if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
209 if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
212 if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
220 "UniPhier DDR PHY parameters dumper",
221 "- dump all of the followings\n"
222 "ddr wbdl - dump Write Bit Delay\n"
223 "ddr rbdl - dump Read Bit Delay\n"
224 "ddr wld - dump Write Leveling\n"
225 "ddr dqsgd - dump DQS Gating Delay\n"
226 "ddr mdl - dump Master Delay Line\n"
227 "ddr reg - dump registers\n"