2 * On-chip UART initializaion for low-level debugging
4 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <linux/serial_reg.h>
10 #include <linux/linkage.h>
11 #include <mach/bcu-regs.h>
12 #include <mach/sc-regs.h>
13 #include <mach/sg-regs.h>
15 #if !defined(CONFIG_DEBUG_SEMIHOSTING)
16 #include CONFIG_DEBUG_LL_INCLUDE
19 #define BAUDRATE 115200
20 #define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d))
25 and r1, r1, #SG_REVISION_TYPE_MASK
26 mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT
28 #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
29 #define PH1_SLD3_UART_CLK 36864000
33 sg_set_pinsel 64, 1, 4, 4, r0, r1 @ TXD0 -> TXD0
41 orr r1, r1, #SC_CLKCTRL_CEN_PERI
44 ldr r3, =DIV_ROUND(PH1_SLD3_UART_CLK, 16 * BAUDRATE)
49 #if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
50 #define PH1_LD4_UART_CLK 36864000
59 sg_set_pinsel 88, 1, 8, 4, r0, r1 @ HSDOUT6 -> TXD0
61 ldr r3, =DIV_ROUND(PH1_LD4_UART_CLK, 16 * BAUDRATE)
66 #if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
67 #define PH1_PRO4_UART_CLK 73728000
71 sg_set_pinsel 128, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
73 ldr r0, =SG_LOADPINCTRL
79 orr r1, r1, #SC_CLKCTRL_CEN_PERI
82 ldr r3, =DIV_ROUND(PH1_PRO4_UART_CLK, 16 * BAUDRATE)
87 #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
88 #define PH1_SLD8_UART_CLK 80000000
97 sg_set_pinsel 70, 3, 8, 4, r0, r1 @ HSDOUT0 -> TXD0
99 ldr r3, =DIV_ROUND(PH1_SLD8_UART_CLK, 16 * BAUDRATE)
104 #if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
105 #define PH1_PRO5_UART_CLK 73728000
109 sg_set_pinsel 47, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
110 sg_set_pinsel 49, 0, 4, 8, r0, r1 @ TXD1 -> TXD1
111 sg_set_pinsel 51, 0, 4, 8, r0, r1 @ TXD2 -> TXD2
112 sg_set_pinsel 53, 0, 4, 8, r0, r1 @ TXD3 -> TXD3
114 ldr r0, =SG_LOADPINCTRL
120 orr r1, r1, #SC_CLKCTRL_CEN_PERI
123 ldr r3, =DIV_ROUND(PH1_PRO5_UART_CLK, 16 * BAUDRATE)
128 #if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
129 #define PROXSTREAM2_UART_CLK 88900000
138 sg_set_pinsel 217, 8, 8, 4, r0, r1 @ TXD0 -> TXD0
139 sg_set_pinsel 115, 8, 8, 4, r0, r1 @ TXD1 -> TXD1
140 sg_set_pinsel 113, 8, 8, 4, r0, r1 @ TXD2 -> TXD2
141 sg_set_pinsel 219, 8, 8, 4, r0, r1 @ TXD3 -> TXD3
145 orr r1, r1, #SC_CLKCTRL_CEN_PERI
148 ldr r3, =DIV_ROUND(PROXSTREAM2_UART_CLK, 16 * BAUDRATE)
153 #if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
154 #define PH1_LD6B_UART_CLK 88900000
163 sg_set_pinsel 135, 3, 8, 4, r0, r1 @ PORT10 -> TXD0
164 sg_set_pinsel 115, 0, 8, 4, r0, r1 @ TXD1 -> TXD1
165 sg_set_pinsel 113, 2, 8, 4, r0, r1 @ SBO0 -> TXD2
169 orr r1, r1, #SC_CLKCTRL_CEN_PERI
172 ldr r3, =DIV_ROUND(PH1_LD6B_UART_CLK, 16 * BAUDRATE)
180 mov r1, #UART_LCR_WLEN8 << 8
185 ENDPROC(debug_ll_init)