2 * Copyright (C) 2015-2017 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/sizes.h>
12 #include "../soc-info.h"
13 #include "ddrmphy-regs.h"
15 /* Select either decimal or hexadecimal */
17 #define PRINTF_FORMAT "%2d"
19 #define PRINTF_FORMAT "%02x"
24 #define ptr_to_uint(p) ((unsigned int)(unsigned long)(p))
26 #define UNIPHIER_MAX_NR_DDRMPHY 3
28 struct uniphier_ddrmphy_param {
35 } phy[UNIPHIER_MAX_NR_DDRMPHY];
38 static const struct uniphier_ddrmphy_param uniphier_ddrmphy_param[] = {
40 .soc_id = UNIPHIER_PXS2_ID,
43 { .base = 0x5b830000, .nr_zq = 3, .nr_dx = 4, },
44 { .base = 0x5ba30000, .nr_zq = 3, .nr_dx = 4, },
45 { .base = 0x5bc30000, .nr_zq = 2, .nr_dx = 2, },
49 .soc_id = UNIPHIER_LD6B_ID,
52 { .base = 0x5b830000, .nr_zq = 3, .nr_dx = 4, },
53 { .base = 0x5ba30000, .nr_zq = 3, .nr_dx = 4, },
54 { .base = 0x5bc30000, .nr_zq = 2, .nr_dx = 2, },
58 UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_ddrmphy_param, uniphier_ddrmphy_param)
60 static void print_bdl(void __iomem *reg, int n)
65 for (i = 0; i < n; i++)
66 printf(FS PRINTF_FORMAT, (val >> i * 8) & 0x1f);
69 static void dump_loop(const struct uniphier_ddrmphy_param *param,
70 void (*callback)(void __iomem *))
72 void __iomem *phy_base, *dx_base;
75 for (phy = 0; phy < param->nr_phy; phy++) {
76 phy_base = ioremap(param->phy[phy].base, SZ_4K);
77 dx_base = phy_base + MPHY_DX_BASE;
79 for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
80 printf("PHY%dDX%d:", phy, dx);
82 dx_base += MPHY_DX_STRIDE;
90 static void zq_dump(const struct uniphier_ddrmphy_param *param)
92 void __iomem *phy_base, *zq_base;
96 printf("\n--- Impedance Data ---\n");
97 printf(" ZPD ZPU OPD OPU ZDV ODV\n");
99 for (phy = 0; phy < param->nr_phy; phy++) {
100 phy_base = ioremap(param->phy[phy].base, SZ_4K);
101 zq_base = phy_base + MPHY_ZQ_BASE;
103 for (zq = 0; zq < param->phy[phy].nr_zq; zq++) {
104 printf("PHY%dZQ%d:", phy, zq);
106 val = readl(zq_base + MPHY_ZQ_DR);
107 for (i = 0; i < 4; i++) {
108 printf(FS PRINTF_FORMAT, val & 0x7f);
112 val = readl(zq_base + MPHY_ZQ_PR);
113 for (i = 0; i < 2; i++) {
114 printf(FS PRINTF_FORMAT, val & 0xf);
118 zq_base += MPHY_ZQ_STRIDE;
126 static void __wbdl_dump(void __iomem *dx_base)
128 print_bdl(dx_base + MPHY_DX_BDLR0, 4);
129 print_bdl(dx_base + MPHY_DX_BDLR1, 4);
130 print_bdl(dx_base + MPHY_DX_BDLR2, 2);
132 printf(FS "(+" PRINTF_FORMAT ")",
133 readl(dx_base + MPHY_DX_LCDLR1) & 0xff);
136 static void wbdl_dump(const struct uniphier_ddrmphy_param *param)
138 printf("\n--- Write Bit Delay Line ---\n");
139 printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
141 dump_loop(param, &__wbdl_dump);
144 static void __rbdl_dump(void __iomem *dx_base)
146 print_bdl(dx_base + MPHY_DX_BDLR3, 4);
147 print_bdl(dx_base + MPHY_DX_BDLR4, 4);
148 print_bdl(dx_base + MPHY_DX_BDLR5, 1);
150 printf(FS "(+" PRINTF_FORMAT ")",
151 (readl(dx_base + MPHY_DX_LCDLR1) >> 8) & 0xff);
153 printf(FS "(+" PRINTF_FORMAT ")",
154 (readl(dx_base + MPHY_DX_LCDLR1) >> 16) & 0xff);
157 static void rbdl_dump(const struct uniphier_ddrmphy_param *param)
159 printf("\n--- Read Bit Delay Line ---\n");
160 printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD) (RDQSND)\n");
162 dump_loop(param, &__rbdl_dump);
165 static void __wld_dump(void __iomem *dx_base)
168 u32 lcdlr0 = readl(dx_base + MPHY_DX_LCDLR0);
169 u32 gtr = readl(dx_base + MPHY_DX_GTR);
171 for (rank = 0; rank < 4; rank++) {
172 u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
173 u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
175 printf(FS PRINTF_FORMAT "%sT", wld,
176 wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
180 static void wld_dump(const struct uniphier_ddrmphy_param *param)
182 printf("\n--- Write Leveling Delay ---\n");
183 printf(" Rank0 Rank1 Rank2 Rank3\n");
185 dump_loop(param, &__wld_dump);
188 static void __dqsgd_dump(void __iomem *dx_base)
191 u32 lcdlr2 = readl(dx_base + MPHY_DX_LCDLR2);
192 u32 gtr = readl(dx_base + MPHY_DX_GTR);
194 for (rank = 0; rank < 4; rank++) {
195 u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
196 u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
198 printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
202 static void dqsgd_dump(const struct uniphier_ddrmphy_param *param)
204 printf("\n--- DQS Gating Delay ---\n");
205 printf(" Rank0 Rank1 Rank2 Rank3\n");
207 dump_loop(param, &__dqsgd_dump);
210 static void __mdl_dump(void __iomem *dx_base)
213 u32 mdl = readl(dx_base + MPHY_DX_MDLR);
215 for (i = 0; i < 3; i++)
216 printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
219 static void mdl_dump(const struct uniphier_ddrmphy_param *param)
221 printf("\n--- Master Delay Line ---\n");
222 printf(" IPRD TPRD MDLD\n");
224 dump_loop(param, &__mdl_dump);
227 #define REG_DUMP(x) \
228 { int ofst = MPHY_ ## x; void __iomem *reg = phy_base + ofst; \
229 printf("%3d: %-10s: %p : %08x\n", \
230 ofst >> MPHY_SHIFT, #x, reg, readl(reg)); }
232 #define DX_REG_DUMP(dx, x) \
233 { int ofst = MPHY_DX_BASE + MPHY_DX_STRIDE * (dx) + \
235 void __iomem *reg = phy_base + ofst; \
236 printf("%3d: DX%d%-7s: %p : %08x\n", \
237 ofst >> MPHY_SHIFT, (dx), #x, reg, readl(reg)); }
239 static void reg_dump(const struct uniphier_ddrmphy_param *param)
241 void __iomem *phy_base;
244 printf("\n--- DDR Multi PHY registers ---\n");
246 for (phy = 0; phy < param->nr_phy; phy++) {
247 phy_base = ioremap(param->phy[phy].base, SZ_4K);
249 printf("== PHY%d (base: %08x) ==\n", phy,
250 ptr_to_uint(phy_base));
251 printf(" No: Name : Address : Data\n");
281 for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
282 DX_REG_DUMP(dx, GCR0);
283 DX_REG_DUMP(dx, GCR1);
284 DX_REG_DUMP(dx, GCR2);
285 DX_REG_DUMP(dx, GCR3);
286 DX_REG_DUMP(dx, GTR);
293 static int do_ddrm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
295 const struct uniphier_ddrmphy_param *param;
298 param = uniphier_get_ddrmphy_param();
300 printf("unsupported SoC\n");
301 return CMD_RET_FAILURE;
309 if (!strcmp(cmd, "zq") || !strcmp(cmd, "all"))
312 if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
315 if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
318 if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
321 if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
324 if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
327 if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
330 return CMD_RET_SUCCESS;
335 "UniPhier DDR Multi PHY parameters dumper",
336 "- dump all of the following\n"
337 "ddrm zq - dump Impedance Data\n"
338 "ddrm wbdl - dump Write Bit Delay\n"
339 "ddrm rbdl - dump Read Bit Delay\n"
340 "ddrm wld - dump Write Leveling\n"
341 "ddrm dqsgd - dump DQS Gating Delay\n"
342 "ddrm mdl - dump Master Delay Line\n"
343 "ddrm reg - dump registers\n"