2 * Copyright (C) 2014 Panasonic Corporation
3 * Copyright (C) 2015-2017 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/sizes.h>
13 #include "../soc-info.h"
14 #include "ddrphy-regs.h"
16 /* Select either decimal or hexadecimal */
18 #define PRINTF_FORMAT "%2d"
20 #define PRINTF_FORMAT "%02x"
25 #define ptr_to_uint(p) ((unsigned int)(unsigned long)(p))
27 #define UNIPHIER_MAX_NR_DDRPHY 4
29 struct uniphier_ddrphy_param {
35 } phy[UNIPHIER_MAX_NR_DDRPHY];
38 static const struct uniphier_ddrphy_param uniphier_ddrphy_param[] = {
40 .soc_id = UNIPHIER_LD4_ID,
43 { .base = 0x5bc01000, .nr_dx = 2, },
44 { .base = 0x5be01000, .nr_dx = 2, },
48 .soc_id = UNIPHIER_PRO4_ID,
51 { .base = 0x5bc01000, .nr_dx = 2, },
52 { .base = 0x5bc02000, .nr_dx = 2, },
53 { .base = 0x5be01000, .nr_dx = 2, },
54 { .base = 0x5be02000, .nr_dx = 2, },
58 .soc_id = UNIPHIER_SLD8_ID,
61 { .base = 0x5bc01000, .nr_dx = 2, },
62 { .base = 0x5be01000, .nr_dx = 2, },
66 .soc_id = UNIPHIER_LD11_ID,
69 { .base = 0x5bc01000, .nr_dx = 4, },
73 UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_ddrphy_param, uniphier_ddrphy_param)
75 static void print_bdl(void __iomem *reg, int n)
80 for (i = 0; i < n; i++)
81 printf(FS PRINTF_FORMAT, (val >> i * 6) & 0x3f);
84 static void dump_loop(const struct uniphier_ddrphy_param *param,
85 void (*callback)(void __iomem *))
87 void __iomem *phy_base, *dx_base;
90 for (phy = 0; phy < param->nr_phy; phy++) {
91 phy_base = ioremap(param->phy[phy].base, SZ_4K);
92 dx_base = phy_base + PHY_DX_BASE;
94 for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
95 printf("PHY%dDX%d:", phy, dx);
97 dx_base += PHY_DX_STRIDE;
105 static void __wbdl_dump(void __iomem *dx_base)
107 print_bdl(dx_base + PHY_DX_BDLR0, 5);
108 print_bdl(dx_base + PHY_DX_BDLR1, 5);
110 printf(FS "(+" PRINTF_FORMAT ")",
111 readl(dx_base + PHY_DX_LCDLR1) & 0xff);
114 static void wbdl_dump(const struct uniphier_ddrphy_param *param)
116 printf("\n--- Write Bit Delay Line ---\n");
117 printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
119 dump_loop(param, &__wbdl_dump);
122 static void __rbdl_dump(void __iomem *dx_base)
124 print_bdl(dx_base + PHY_DX_BDLR3, 5);
125 print_bdl(dx_base + PHY_DX_BDLR4, 4);
127 printf(FS "(+" PRINTF_FORMAT ")",
128 (readl(dx_base + PHY_DX_LCDLR1) >> 8) & 0xff);
131 static void rbdl_dump(const struct uniphier_ddrphy_param *param)
133 printf("\n--- Read Bit Delay Line ---\n");
134 printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
136 dump_loop(param, &__rbdl_dump);
139 static void __wld_dump(void __iomem *dx_base)
142 u32 lcdlr0 = readl(dx_base + PHY_DX_LCDLR0);
143 u32 gtr = readl(dx_base + PHY_DX_GTR);
145 for (rank = 0; rank < 4; rank++) {
146 u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
147 u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
149 printf(FS PRINTF_FORMAT "%sT", wld,
150 wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
154 static void wld_dump(const struct uniphier_ddrphy_param *param)
156 printf("\n--- Write Leveling Delay ---\n");
157 printf(" Rank0 Rank1 Rank2 Rank3\n");
159 dump_loop(param, &__wld_dump);
162 static void __dqsgd_dump(void __iomem *dx_base)
165 u32 lcdlr2 = readl(dx_base + PHY_DX_LCDLR2);
166 u32 gtr = readl(dx_base + PHY_DX_GTR);
168 for (rank = 0; rank < 4; rank++) {
169 u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
170 u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
172 printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
176 static void dqsgd_dump(const struct uniphier_ddrphy_param *param)
178 printf("\n--- DQS Gating Delay ---\n");
179 printf(" Rank0 Rank1 Rank2 Rank3\n");
181 dump_loop(param, &__dqsgd_dump);
184 static void __mdl_dump(void __iomem *dx_base)
187 u32 mdl = readl(dx_base + PHY_DX_MDLR);
189 for (i = 0; i < 3; i++)
190 printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
193 static void mdl_dump(const struct uniphier_ddrphy_param *param)
195 printf("\n--- Master Delay Line ---\n");
196 printf(" IPRD TPRD MDLD\n");
198 dump_loop(param, &__mdl_dump);
201 #define REG_DUMP(x) \
202 { int ofst = PHY_ ## x; void __iomem *reg = phy_base + ofst; \
203 printf("%3d: %-10s: %08x : %08x\n", \
204 ofst >> PHY_REG_SHIFT, #x, \
205 ptr_to_uint(reg), readl(reg)); }
207 #define DX_REG_DUMP(dx, x) \
208 { int ofst = PHY_DX_BASE + PHY_DX_STRIDE * (dx) + \
210 void __iomem *reg = phy_base + ofst; \
211 printf("%3d: DX%d%-7s: %08x : %08x\n", \
212 ofst >> PHY_REG_SHIFT, (dx), #x, \
213 ptr_to_uint(reg), readl(reg)); }
215 static void reg_dump(const struct uniphier_ddrphy_param *param)
217 void __iomem *phy_base;
220 printf("\n--- DDR PHY registers ---\n");
222 for (phy = 0; phy < param->nr_phy; phy++) {
223 phy_base = ioremap(param->phy[phy].base, SZ_4K);
225 printf("== PHY%d (base: %08x) ==\n",
226 phy, ptr_to_uint(phy_base));
227 printf(" No: Name : Address : Data\n");
254 for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
255 DX_REG_DUMP(dx, GCR);
256 DX_REG_DUMP(dx, GTR);
263 static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
265 const struct uniphier_ddrphy_param *param;
268 param = uniphier_get_ddrphy_param();
270 printf("unsupported SoC\n");
271 return CMD_RET_FAILURE;
279 if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
282 if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
285 if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
288 if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
291 if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
294 if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
297 return CMD_RET_SUCCESS;
302 "UniPhier DDR PHY parameters dumper",
303 "- dump all of the following\n"
304 "ddr wbdl - dump Write Bit Delay\n"
305 "ddr rbdl - dump Read Bit Delay\n"
306 "ddr wld - dump Write Leveling\n"
307 "ddr dqsgd - dump DQS Gating Delay\n"
308 "ddr mdl - dump Master Delay Line\n"
309 "ddr reg - dump registers\n"