2 * Copyright (C) 2014 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/sizes.h>
13 #include "../soc-info.h"
14 #include "ddrphy-init.h"
15 #include "ddrphy-regs.h"
17 /* Select either decimal or hexadecimal */
19 #define PRINTF_FORMAT "%2d"
21 #define PRINTF_FORMAT "%02x"
26 static unsigned long uniphier_ld4_base[] = {
32 static unsigned long uniphier_pro4_base[] = {
38 static unsigned long uniphier_sld8_base[] = {
44 static void print_bdl(void __iomem *reg, int n)
49 for (i = 0; i < n; i++)
50 printf(FS PRINTF_FORMAT, (val >> i * 6) & 0x3f);
53 static void dump_loop(unsigned long *base,
54 void (*callback)(void __iomem *))
56 void __iomem *phy_base, *dx_base;
59 for (p = 0; *base; base++, p++) {
60 phy_base = ioremap(*base, SZ_4K);
61 dx_base = phy_base + PHY_DX_BASE;
63 for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
64 printf("PHY%dDX%d:", p, dx);
66 dx_base += PHY_DX_STRIDE;
74 static void __wbdl_dump(void __iomem *dx_base)
76 print_bdl(dx_base + PHY_DX_BDLR0, 5);
77 print_bdl(dx_base + PHY_DX_BDLR1, 5);
79 printf(FS "(+" PRINTF_FORMAT ")",
80 readl(dx_base + PHY_DX_LCDLR1) & 0xff);
83 static void wbdl_dump(unsigned long *base)
85 printf("\n--- Write Bit Delay Line ---\n");
86 printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
88 dump_loop(base, &__wbdl_dump);
91 static void __rbdl_dump(void __iomem *dx_base)
93 print_bdl(dx_base + PHY_DX_BDLR3, 5);
94 print_bdl(dx_base + PHY_DX_BDLR4, 4);
96 printf(FS "(+" PRINTF_FORMAT ")",
97 (readl(dx_base + PHY_DX_LCDLR1) >> 8) & 0xff);
100 static void rbdl_dump(unsigned long *base)
102 printf("\n--- Read Bit Delay Line ---\n");
103 printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
105 dump_loop(base, &__rbdl_dump);
108 static void __wld_dump(void __iomem *dx_base)
111 u32 lcdlr0 = readl(dx_base + PHY_DX_LCDLR0);
112 u32 gtr = readl(dx_base + PHY_DX_GTR);
114 for (rank = 0; rank < 4; rank++) {
115 u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
116 u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
118 printf(FS PRINTF_FORMAT "%sT", wld,
119 wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
123 static void wld_dump(unsigned long *base)
125 printf("\n--- Write Leveling Delay ---\n");
126 printf(" Rank0 Rank1 Rank2 Rank3\n");
128 dump_loop(base, &__wld_dump);
131 static void __dqsgd_dump(void __iomem *dx_base)
134 u32 lcdlr2 = readl(dx_base + PHY_DX_LCDLR2);
135 u32 gtr = readl(dx_base + PHY_DX_GTR);
137 for (rank = 0; rank < 4; rank++) {
138 u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
139 u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
141 printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
145 static void dqsgd_dump(unsigned long *base)
147 printf("\n--- DQS Gating Delay ---\n");
148 printf(" Rank0 Rank1 Rank2 Rank3\n");
150 dump_loop(base, &__dqsgd_dump);
153 static void __mdl_dump(void __iomem *dx_base)
156 u32 mdl = readl(dx_base + PHY_DX_MDLR);
157 for (i = 0; i < 3; i++)
158 printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
161 static void mdl_dump(unsigned long *base)
163 printf("\n--- Master Delay Line ---\n");
164 printf(" IPRD TPRD MDLD\n");
166 dump_loop(base, &__mdl_dump);
169 #define REG_DUMP(x) \
170 { int ofst = PHY_ ## x; void __iomem *reg = phy_base + ofst; \
171 printf("%3d: %-10s: %p : %08x\n", \
172 ofst >> PHY_REG_SHIFT, #x, reg, readl(reg)); }
174 #define DX_REG_DUMP(dx, x) \
175 { int ofst = PHY_DX_BASE + PHY_DX_STRIDE * (dx) + \
177 void __iomem *reg = phy_base + ofst; \
178 printf("%3d: DX%d%-7s: %p : %08x\n", \
179 ofst >> PHY_REG_SHIFT, (dx), #x, reg, readl(reg)); }
181 static void reg_dump(unsigned long *base)
183 void __iomem *phy_base;
186 printf("\n--- DDR PHY registers ---\n");
188 for (p = 0; *base; base++, p++) {
189 phy_base = ioremap(*base, SZ_4K);
191 printf("== PHY%d (base: %p) ==\n", p, phy_base);
192 printf(" No: Name : Address : Data\n");
219 for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
220 DX_REG_DUMP(dx, GCR);
221 DX_REG_DUMP(dx, GTR);
228 static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
233 switch (uniphier_get_soc_type()) {
234 case SOC_UNIPHIER_LD4:
235 base = uniphier_ld4_base;
237 case SOC_UNIPHIER_PRO4:
238 base = uniphier_pro4_base;
240 case SOC_UNIPHIER_SLD8:
241 base = uniphier_sld8_base;
244 printf("unsupported SoC\n");
245 return CMD_RET_FAILURE;
251 if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
254 if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
257 if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
260 if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
263 if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
266 if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
269 return CMD_RET_SUCCESS;
274 "UniPhier DDR PHY parameters dumper",
275 "- dump all of the following\n"
276 "ddr wbdl - dump Write Bit Delay\n"
277 "ddr rbdl - dump Read Bit Delay\n"
278 "ddr wld - dump Write Leveling\n"
279 "ddr dqsgd - dump DQS Gating Delay\n"
280 "ddr mdl - dump Master Delay Line\n"
281 "ddr reg - dump registers\n"