1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014 Panasonic Corporation
4 * Copyright (C) 2015-2017 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
11 #include <linux/printk.h>
12 #include <linux/sizes.h>
14 #include "../soc-info.h"
15 #include "ddrphy-regs.h"
17 /* Select either decimal or hexadecimal */
19 #define PRINTF_FORMAT "%2d"
21 #define PRINTF_FORMAT "%02x"
26 #define ptr_to_uint(p) ((unsigned int)(unsigned long)(p))
28 #define UNIPHIER_MAX_NR_DDRPHY 4
30 struct uniphier_ddrphy_param {
36 } phy[UNIPHIER_MAX_NR_DDRPHY];
39 static const struct uniphier_ddrphy_param uniphier_ddrphy_param[] = {
41 .soc_id = UNIPHIER_LD4_ID,
44 { .base = 0x5bc01000, .nr_dx = 2, },
45 { .base = 0x5be01000, .nr_dx = 2, },
49 .soc_id = UNIPHIER_PRO4_ID,
52 { .base = 0x5bc01000, .nr_dx = 2, },
53 { .base = 0x5bc02000, .nr_dx = 2, },
54 { .base = 0x5be01000, .nr_dx = 2, },
55 { .base = 0x5be02000, .nr_dx = 2, },
59 .soc_id = UNIPHIER_SLD8_ID,
62 { .base = 0x5bc01000, .nr_dx = 2, },
63 { .base = 0x5be01000, .nr_dx = 2, },
67 .soc_id = UNIPHIER_LD11_ID,
70 { .base = 0x5bc01000, .nr_dx = 4, },
74 UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_ddrphy_param, uniphier_ddrphy_param)
76 static void print_bdl(void __iomem *reg, int n)
81 for (i = 0; i < n; i++)
82 printf(FS PRINTF_FORMAT, (val >> i * 6) & 0x3f);
85 static void dump_loop(const struct uniphier_ddrphy_param *param,
86 void (*callback)(void __iomem *))
88 void __iomem *phy_base, *dx_base;
91 for (phy = 0; phy < param->nr_phy; phy++) {
92 phy_base = ioremap(param->phy[phy].base, SZ_4K);
93 dx_base = phy_base + PHY_DX_BASE;
95 for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
96 printf("PHY%dDX%d:", phy, dx);
98 dx_base += PHY_DX_STRIDE;
106 static void __wbdl_dump(void __iomem *dx_base)
108 print_bdl(dx_base + PHY_DX_BDLR0, 5);
109 print_bdl(dx_base + PHY_DX_BDLR1, 5);
111 printf(FS "(+" PRINTF_FORMAT ")",
112 readl(dx_base + PHY_DX_LCDLR1) & 0xff);
115 static void wbdl_dump(const struct uniphier_ddrphy_param *param)
117 printf("\n--- Write Bit Delay Line ---\n");
118 printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
120 dump_loop(param, &__wbdl_dump);
123 static void __rbdl_dump(void __iomem *dx_base)
125 print_bdl(dx_base + PHY_DX_BDLR3, 5);
126 print_bdl(dx_base + PHY_DX_BDLR4, 4);
128 printf(FS "(+" PRINTF_FORMAT ")",
129 (readl(dx_base + PHY_DX_LCDLR1) >> 8) & 0xff);
132 static void rbdl_dump(const struct uniphier_ddrphy_param *param)
134 printf("\n--- Read Bit Delay Line ---\n");
135 printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
137 dump_loop(param, &__rbdl_dump);
140 static void __wld_dump(void __iomem *dx_base)
143 u32 lcdlr0 = readl(dx_base + PHY_DX_LCDLR0);
144 u32 gtr = readl(dx_base + PHY_DX_GTR);
146 for (rank = 0; rank < 4; rank++) {
147 u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
148 u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
150 printf(FS PRINTF_FORMAT "%sT", wld,
151 wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
155 static void wld_dump(const struct uniphier_ddrphy_param *param)
157 printf("\n--- Write Leveling Delay ---\n");
158 printf(" Rank0 Rank1 Rank2 Rank3\n");
160 dump_loop(param, &__wld_dump);
163 static void __dqsgd_dump(void __iomem *dx_base)
166 u32 lcdlr2 = readl(dx_base + PHY_DX_LCDLR2);
167 u32 gtr = readl(dx_base + PHY_DX_GTR);
169 for (rank = 0; rank < 4; rank++) {
170 u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
171 u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
173 printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
177 static void dqsgd_dump(const struct uniphier_ddrphy_param *param)
179 printf("\n--- DQS Gating Delay ---\n");
180 printf(" Rank0 Rank1 Rank2 Rank3\n");
182 dump_loop(param, &__dqsgd_dump);
185 static void __mdl_dump(void __iomem *dx_base)
188 u32 mdl = readl(dx_base + PHY_DX_MDLR);
190 for (i = 0; i < 3; i++)
191 printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
194 static void mdl_dump(const struct uniphier_ddrphy_param *param)
196 printf("\n--- Master Delay Line ---\n");
197 printf(" IPRD TPRD MDLD\n");
199 dump_loop(param, &__mdl_dump);
202 #define REG_DUMP(x) \
203 { int ofst = PHY_ ## x; void __iomem *reg = phy_base + ofst; \
204 printf("%3d: %-10s: %08x : %08x\n", \
205 ofst >> PHY_REG_SHIFT, #x, \
206 ptr_to_uint(reg), readl(reg)); }
208 #define DX_REG_DUMP(dx, x) \
209 { int ofst = PHY_DX_BASE + PHY_DX_STRIDE * (dx) + \
211 void __iomem *reg = phy_base + ofst; \
212 printf("%3d: DX%d%-7s: %08x : %08x\n", \
213 ofst >> PHY_REG_SHIFT, (dx), #x, \
214 ptr_to_uint(reg), readl(reg)); }
216 static void reg_dump(const struct uniphier_ddrphy_param *param)
218 void __iomem *phy_base;
221 printf("\n--- DDR PHY registers ---\n");
223 for (phy = 0; phy < param->nr_phy; phy++) {
224 phy_base = ioremap(param->phy[phy].base, SZ_4K);
226 printf("== PHY%d (base: %08x) ==\n",
227 phy, ptr_to_uint(phy_base));
228 printf(" No: Name : Address : Data\n");
255 for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
256 DX_REG_DUMP(dx, GCR);
257 DX_REG_DUMP(dx, GTR);
264 static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
266 const struct uniphier_ddrphy_param *param;
269 param = uniphier_get_ddrphy_param();
271 pr_err("unsupported SoC\n");
272 return CMD_RET_FAILURE;
280 if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
283 if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
286 if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
289 if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
292 if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
295 if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
298 return CMD_RET_SUCCESS;
303 "UniPhier DDR PHY parameters dumper",
304 "- dump all of the following\n"
305 "ddr wbdl - dump Write Bit Delay\n"
306 "ddr rbdl - dump Read Bit Delay\n"
307 "ddr wld - dump Write Leveling\n"
308 "ddr dqsgd - dump DQS Gating Delay\n"
309 "ddr mdl - dump Master Delay Line\n"
310 "ddr reg - dump registers\n"