2 * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * SPDX-License-Identifier: GPL-2.0+
11 #include "ddrphy-regs.h"
13 void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank)
18 for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
22 /* Specify the rank that should be write leveled */
23 tmp &= ~DXGCR_WLRKEN_MASK;
24 tmp |= (1 << (DXGCR_WLRKEN_SHIFT + rank)) & DXGCR_WLRKEN_MASK;
31 /* Specify the rank used during data bit deskew and eye centering */
32 tmp &= ~DTCR_DTRANK_MASK;
33 tmp |= (rank << DTCR_DTRANK_SHIFT) & DTCR_DTRANK_MASK;
34 /* Use Multi-Purpose Register for DQS gate training */
36 /* Specify the rank enabled for data-training */
37 tmp &= ~DTCR_RANKEN_MASK;
38 tmp |= (1 << (DTCR_RANKEN_SHIFT + rank)) & DTCR_RANKEN_MASK;
42 struct ddrphy_init_sequence {
49 static const struct ddrphy_init_sequence init_sequence[] = {
51 "DRAM Initialization",
52 PIR_DRAMRST | PIR_DRAMINIT,
63 "Read DQS Gate Training",
69 "Write Leveling Adjustment",
100 int ddrphy_training(struct ddrphy __iomem *phy)
104 u32 init_flag = PIR_INIT;
105 u32 done_flag = PGSR0_IDONE;
106 int timeout = 50000; /* 50 msec is long enough */
107 #ifdef DISPLAY_ELAPSED_TIME
108 ulong start = get_timer(0);
111 for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
112 init_flag |= init_sequence[i].init_flag;
113 done_flag |= init_sequence[i].done_flag;
116 writel(init_flag, &phy->pir);
120 printf("%s: error: timeout during DDR training\n",
125 pgsr0 = readl(&phy->pgsr[0]);
126 } while ((pgsr0 & done_flag) != done_flag);
128 for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
129 if (pgsr0 & init_sequence[i].err_flag) {
130 printf("%s: error: %s failed\n", __func__,
131 init_sequence[i].description);
136 #ifdef DISPLAY_ELAPSED_TIME
137 printf("%s: info: elapsed time %ld msec\n", get_timer(start));