1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2011-2014 Panasonic Corporation
4 * Copyright (C) 2015-2016 Socionext Inc.
7 #include <linux/bitops.h>
8 #include <linux/delay.h>
9 #include <linux/errno.h>
11 #include <linux/kernel.h>
12 #include <linux/printk.h>
15 #include "ddrphy-init.h"
16 #include "ddrphy-regs.h"
18 /* for LD4, Pro4, sLD8 */
19 #define NR_DATX8_PER_DDRPHY 2
21 void ddrphy_prepare_training(void __iomem *phy_base, int rank)
23 void __iomem *dx_base = phy_base + PHY_DX_BASE;
27 for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
28 tmp = readl(dx_base + PHY_DX_GCR);
29 /* Specify the rank that should be write leveled */
30 tmp &= ~PHY_DX_GCR_WLRKEN_MASK;
31 tmp |= (1 << (PHY_DX_GCR_WLRKEN_SHIFT + rank)) &
32 PHY_DX_GCR_WLRKEN_MASK;
33 writel(tmp, dx_base + PHY_DX_GCR);
34 dx_base += PHY_DX_STRIDE;
37 tmp = readl(phy_base + PHY_DTCR);
38 /* Specify the rank used during data bit deskew and eye centering */
39 tmp &= ~PHY_DTCR_DTRANK_MASK;
40 tmp |= (rank << PHY_DTCR_DTRANK_SHIFT) & PHY_DTCR_DTRANK_MASK;
41 /* Use Multi-Purpose Register for DQS gate training */
42 tmp |= PHY_DTCR_DTMPR;
43 /* Specify the rank enabled for data-training */
44 tmp &= ~PHY_DTCR_RANKEN_MASK;
45 tmp |= (1 << (PHY_DTCR_RANKEN_SHIFT + rank)) & PHY_DTCR_RANKEN_MASK;
46 writel(tmp, phy_base + PHY_DTCR);
49 struct ddrphy_init_sequence {
56 static const struct ddrphy_init_sequence init_sequence[] = {
58 "DRAM Initialization",
59 PHY_PIR_DRAMRST | PHY_PIR_DRAMINIT,
70 "Read DQS Gate Training",
76 "Write Leveling Adjustment",
100 "Write Eye Training",
107 int ddrphy_training(void __iomem *phy_base)
111 u32 init_flag = PHY_PIR_INIT;
112 u32 done_flag = PHY_PGSR0_IDONE;
113 int timeout = 50000; /* 50 msec is long enough */
115 ulong start = get_timer(0);
118 for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
119 init_flag |= init_sequence[i].init_flag;
120 done_flag |= init_sequence[i].done_flag;
123 writel(init_flag, phy_base + PHY_PIR);
127 pr_err("timeout during DDR training\n");
131 pgsr0 = readl(phy_base + PHY_PGSR0);
132 } while ((pgsr0 & done_flag) != done_flag);
134 for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
135 if (pgsr0 & init_sequence[i].err_flag) {
136 pr_err("%s failed\n", init_sequence[i].description);
142 pr_debug("DDR training: elapsed time %ld msec\n", get_timer(start));