git.sur5r.net Git - u-boot/blob - arch/arm/mach-uniphier/dram/umc-ph1-ld4.c

   1 /*
   2  * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <linux/err.h>
   9 #include <linux/io.h>
  10 #include <linux/sizes.h>
  11
  12 #include "../init.h"
  13 #include "ddrphy-regs.h"
  14 #include "umc-regs.h"
  15
  16 static void umc_start_ssif(void __iomem *ssif_base)
  17 {
  18         writel(0x00000000, ssif_base + 0x0000b004);
  19         writel(0xffffffff, ssif_base + 0x0000c004);
  20         writel(0x000fffcf, ssif_base + 0x0000c008);
  21         writel(0x00000001, ssif_base + 0x0000b000);
  22         writel(0x00000001, ssif_base + 0x0000c000);
  23         writel(0x03010101, ssif_base + UMC_MDMCHSEL);
  24         writel(0x03010100, ssif_base + UMC_DMDCHSEL);
  25
  26         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
  27         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
  28         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
  29         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
  30         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
  31         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
  32         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
  33         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
  34         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
  35         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
  36
  37         writel(0x00000001, ssif_base + UMC_CPURST);
  38         writel(0x00000001, ssif_base + UMC_IDSRST);
  39         writel(0x00000001, ssif_base + UMC_IXMRST);
  40         writel(0x00000001, ssif_base + UMC_MDMRST);
  41         writel(0x00000001, ssif_base + UMC_MDDRST);
  42         writel(0x00000001, ssif_base + UMC_SIORST);
  43         writel(0x00000001, ssif_base + UMC_VIORST);
  44         writel(0x00000001, ssif_base + UMC_FRCRST);
  45         writel(0x00000001, ssif_base + UMC_RGLRST);
  46         writel(0x00000001, ssif_base + UMC_AIORST);
  47         writel(0x00000001, ssif_base + UMC_DMDRST);
  48 }
  49
  50 static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
  51                               int size, int freq)
  52 {
  53         if (freq == 1333) {
  54                 writel(0x45990b11, dramcont + UMC_CMDCTLA);
  55                 writel(0x16958924, dramcont + UMC_CMDCTLB);
  56         } else if (freq == 1600) {
  57                 writel(0x36BB0F17, dramcont + UMC_CMDCTLA);
  58                 writel(0x18C6AA24, dramcont + UMC_CMDCTLB);
  59         }
  60
  61         if (freq == 1333) {
  62                 if (size == 1)
  63                         writel(0x00240512, dramcont + UMC_SPCCTLA);
  64                 else if (size == 2)
  65                         writel(0x00350512, dramcont + UMC_SPCCTLA);
  66
  67                 writel(0x00ff0006, dramcont + UMC_SPCCTLB);
  68                 writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
  69         } else if (freq == 1600) {
  70                 if (size == 1)
  71                         writel(0x002B0617, dramcont + UMC_SPCCTLA);
  72                 else if (size == 2)
  73                         writel(0x003F0617, dramcont + UMC_SPCCTLA);
  74
  75                 writel(0x00ff0008, dramcont + UMC_SPCCTLB);
  76                 writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
  77         }
  78
  79         writel(0x04060806, dramcont + UMC_WDATACTL_D0);
  80         writel(0x04a02000, dramcont + UMC_DATASET);
  81         writel(0x00000000, ca_base + 0x2300);
  82         writel(0x00400020, dramcont + UMC_DCCGCTL);
  83         writel(0x00000003, dramcont + 0x7000);
  84         writel(0x0000000f, dramcont + 0x8000);
  85         writel(0x000000c3, dramcont + 0x8004);
  86         writel(0x00000071, dramcont + 0x8008);
  87         writel(0x0000003b, dramcont + UMC_DICGCTLA);
  88         writel(0x020a0808, dramcont + UMC_DICGCTLB);
  89         writel(0x00000004, dramcont + UMC_FLOWCTLG);
  90         writel(0x80000201, ca_base + 0xc20);
  91         writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
  92         writel(0x00200000, dramcont + UMC_FLOWCTLB);
  93         writel(0x00004444, dramcont + UMC_FLOWCTLC);
  94         writel(0x200a0a00, dramcont + UMC_SPCSETB);
  95         writel(0x00000000, dramcont + UMC_SPCSETD);
  96         writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
  97 }
  98
  99 static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus)
 100 {
 101         void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
 102         void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
 103         void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
 104         void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
 105         void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
 106         void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
 107         void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
 108
 109         umc_dram_init_start(dramcont0);
 110         umc_dram_init_start(dramcont1);
 111         umc_dram_init_poll(dramcont0);
 112         umc_dram_init_poll(dramcont1);
 113
 114         writel(0x00000101, dramcont0 + UMC_DIOCTLA);
 115
 116         ph1_ld4_ddrphy_init(phy0_0, freq, ddr3plus);
 117
 118         ddrphy_prepare_training(phy0_0, 0);
 119         ddrphy_training(phy0_0);
 120
 121         writel(0x00000101, dramcont1 + UMC_DIOCTLA);
 122
 123         ph1_ld4_ddrphy_init(phy1_0, freq, ddr3plus);
 124
 125         ddrphy_prepare_training(phy1_0, 1);
 126         ddrphy_training(phy1_0);
 127
 128         umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
 129         umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
 130
 131         umc_start_ssif(ssif_base);
 132
 133         return 0;
 134 }
 135
 136 int ph1_ld4_umc_init(const struct uniphier_board_data *bd)
 137 {
 138         if ((bd->dram_ch[0].size == SZ_128M || bd->dram_ch[0].size == SZ_256M) &&
 139             (bd->dram_ch[1].size == SZ_128M || bd->dram_ch[1].size == SZ_256M) &&
 140             (bd->dram_freq == 1333 || bd->dram_freq == 1600) &&
 141             bd->dram_ch[0].width == 16 && bd->dram_ch[1].width == 16) {
 142                 return umc_init_sub(bd->dram_freq,
 143                                     bd->dram_ch[0].size / SZ_128M,
 144                                     bd->dram_ch[1].size / SZ_128M,
 145                                     bd->dram_ddr3plus);
 146         } else {
 147                 pr_err("Unsupported DDR configuration\n");
 148                 return -EINVAL;
 149         }
 150 }