git.sur5r.net Git - u-boot/blob - arch/arm/mach-uniphier/dram/umc-ph1-pro4.c

   1 /*
   2  * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <linux/err.h>
   9 #include <linux/io.h>
  10 #include <linux/sizes.h>
  11
  12 #include "../init.h"
  13 #include "ddrphy-regs.h"
  14 #include "umc-regs.h"
  15
  16 enum dram_size {
  17         DRAM_SZ_128M,
  18         DRAM_SZ_256M,
  19         DRAM_SZ_512M,
  20         DRAM_SZ_NR,
  21 };
  22
  23 static u32 umc_initctlb[DRAM_SZ_NR] = {0x43030d3f, 0x43030d3f, 0x7b030d3f};
  24 static u32 umc_spcctla[DRAM_SZ_NR] = {0x002b0617, 0x003f0617, 0x00770617};
  25
  26 static void umc_start_ssif(void __iomem *ssif_base)
  27 {
  28         writel(0x00000001, ssif_base + 0x0000b004);
  29         writel(0xffffffff, ssif_base + 0x0000c004);
  30         writel(0x07ffffff, ssif_base + 0x0000c008);
  31         writel(0x00000001, ssif_base + 0x0000b000);
  32         writel(0x00000001, ssif_base + 0x0000c000);
  33
  34         writel(0x03010100, ssif_base + UMC_HDMCHSEL);
  35         writel(0x03010101, ssif_base + UMC_MDMCHSEL);
  36         writel(0x03010100, ssif_base + UMC_DVCCHSEL);
  37         writel(0x03010100, ssif_base + UMC_DMDCHSEL);
  38
  39         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
  40         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
  41         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
  42         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
  43         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
  44         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
  45         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
  46         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
  47         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
  48         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
  49         writel(0x00000000, ssif_base + 0x0000c044);             /* DCGIV_SSIF_REG */
  50
  51         writel(0x00000001, ssif_base + UMC_CPURST);
  52         writel(0x00000001, ssif_base + UMC_IDSRST);
  53         writel(0x00000001, ssif_base + UMC_IXMRST);
  54         writel(0x00000001, ssif_base + UMC_HDMRST);
  55         writel(0x00000001, ssif_base + UMC_MDMRST);
  56         writel(0x00000001, ssif_base + UMC_HDDRST);
  57         writel(0x00000001, ssif_base + UMC_MDDRST);
  58         writel(0x00000001, ssif_base + UMC_SIORST);
  59         writel(0x00000001, ssif_base + UMC_GIORST);
  60         writel(0x00000001, ssif_base + UMC_HD2RST);
  61         writel(0x00000001, ssif_base + UMC_VIORST);
  62         writel(0x00000001, ssif_base + UMC_DVCRST);
  63         writel(0x00000001, ssif_base + UMC_RGLRST);
  64         writel(0x00000001, ssif_base + UMC_VPERST);
  65         writel(0x00000001, ssif_base + UMC_AIORST);
  66         writel(0x00000001, ssif_base + UMC_DMDRST);
  67 }
  68
  69 static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
  70                              int size, int width)
  71 {
  72         enum dram_size dram_size;
  73
  74         switch (size / (width / 16)) {
  75         case SZ_128M:
  76                 dram_size = DRAM_SZ_128M;
  77                 break;
  78         case SZ_256M:
  79                 dram_size = DRAM_SZ_256M;
  80                 break;
  81         case SZ_512M:
  82                 dram_size = DRAM_SZ_512M;
  83                 break;
  84         default:
  85                 printf("unsupported DRAM size\n");
  86                 return -EINVAL;
  87         }
  88
  89         writel(0x66bb0f17, dramcont + UMC_CMDCTLA);
  90         writel(0x18c6aa44, dramcont + UMC_CMDCTLB);
  91         writel(0x5101387f, dramcont + UMC_INITCTLA);
  92         writel(umc_initctlb[dram_size], dramcont + UMC_INITCTLB);
  93         writel(0x00ff00ff, dramcont + UMC_INITCTLC);
  94         writel(0x00000d71, dramcont + UMC_DRMMR0);
  95         writel(0x00000006, dramcont + UMC_DRMMR1);
  96         writel(0x00000298, dramcont + UMC_DRMMR2);
  97         writel(0x00000000, dramcont + UMC_DRMMR3);
  98         writel(umc_spcctla[dram_size], dramcont + UMC_SPCCTLA);
  99         writel(0x00ff0008, dramcont + UMC_SPCCTLB);
 100         writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
 101         writel(0x000c00ae, dramcont + UMC_RDATACTL_D1);
 102         writel(0x04060802, dramcont + UMC_WDATACTL_D0);
 103         writel(0x04060802, dramcont + UMC_WDATACTL_D1);
 104         writel(0x04a02000, dramcont + UMC_DATASET);
 105         writel(0x00000000, ca_base + 0x2300);
 106         writel(0x00400020, dramcont + UMC_DCCGCTL);
 107         writel(0x0000000f, dramcont + 0x7000);
 108         writel(0x0000000f, dramcont + 0x8000);
 109         writel(0x000000c3, dramcont + 0x8004);
 110         writel(0x00000071, dramcont + 0x8008);
 111         writel(0x00000004, dramcont + UMC_FLOWCTLG);
 112         writel(0x00000000, dramcont + 0x0060);
 113         writel(0x80000201, ca_base + 0xc20);
 114         writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
 115         writel(0x00200000, dramcont + UMC_FLOWCTLB);
 116         writel(0x00004444, dramcont + UMC_FLOWCTLC);
 117         writel(0x200a0a00, dramcont + UMC_SPCSETB);
 118         writel(0x00010000, dramcont + UMC_SPCSETD);
 119         writel(0x80000020, dramcont + UMC_DFICUPDCTLA);
 120
 121         return 0;
 122 }
 123
 124 int ph1_pro4_umc_init(const struct uniphier_board_data *bd)
 125 {
 126         void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
 127         void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
 128         void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
 129         void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
 130         void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
 131         void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
 132         void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1);
 133         void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
 134         void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1);
 135         int ret;
 136
 137         if (bd->dram_freq != 1600) {
 138                 pr_err("Unsupported DDR configuration\n");
 139                 return -EINVAL;
 140         }
 141
 142         umc_dram_init_start(dramcont0);
 143         umc_dram_init_start(dramcont1);
 144         umc_dram_init_poll(dramcont0);
 145         umc_dram_init_poll(dramcont1);
 146
 147         writel(0x00000101, dramcont0 + UMC_DIOCTLA);
 148
 149         ph1_pro4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch0_size);
 150
 151         ddrphy_prepare_training(phy0_0, 0);
 152         ddrphy_training(phy0_0);
 153
 154         writel(0x00000103, dramcont0 + UMC_DIOCTLA);
 155
 156         ph1_pro4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch0_size);
 157
 158         ddrphy_prepare_training(phy0_1, 1);
 159         ddrphy_training(phy0_1);
 160
 161         writel(0x00000101, dramcont1 + UMC_DIOCTLA);
 162
 163         ph1_pro4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch1_size);
 164
 165         ddrphy_prepare_training(phy1_0, 0);
 166         ddrphy_training(phy1_0);
 167
 168         writel(0x00000103, dramcont1 + UMC_DIOCTLA);
 169
 170         ph1_pro4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch1_size);
 171
 172         ddrphy_prepare_training(phy1_1, 1);
 173         ddrphy_training(phy1_1);
 174
 175         ret = umc_dramcont_init(dramcont0, ca_base0, bd->dram_ch0_size,
 176                                 bd->dram_ch0_width);
 177         if (ret)
 178                 return ret;
 179
 180         ret = umc_dramcont_init(dramcont1, ca_base1, bd->dram_ch1_size,
 181                                 bd->dram_ch1_width);
 182         if (ret)
 183                 return ret;
 184
 185         umc_start_ssif(ssif_base);
 186
 187         return 0;
 188 }