2 * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/sizes.h>
13 #include "ddrphy-regs.h"
16 static void umc_start_ssif(void __iomem *ssif_base)
18 writel(0x00000001, ssif_base + 0x0000b004);
19 writel(0xffffffff, ssif_base + 0x0000c004);
20 writel(0x07ffffff, ssif_base + 0x0000c008);
21 writel(0x00000001, ssif_base + 0x0000b000);
22 writel(0x00000001, ssif_base + 0x0000c000);
24 writel(0x03010100, ssif_base + UMC_HDMCHSEL);
25 writel(0x03010101, ssif_base + UMC_MDMCHSEL);
26 writel(0x03010100, ssif_base + UMC_DVCCHSEL);
27 writel(0x03010100, ssif_base + UMC_DMDCHSEL);
29 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
30 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
31 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
32 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
33 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
34 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
35 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
36 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
37 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
38 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
39 writel(0x00000000, ssif_base + 0x0000c044); /* DCGIV_SSIF_REG */
41 writel(0x00000001, ssif_base + UMC_CPURST);
42 writel(0x00000001, ssif_base + UMC_IDSRST);
43 writel(0x00000001, ssif_base + UMC_IXMRST);
44 writel(0x00000001, ssif_base + UMC_HDMRST);
45 writel(0x00000001, ssif_base + UMC_MDMRST);
46 writel(0x00000001, ssif_base + UMC_HDDRST);
47 writel(0x00000001, ssif_base + UMC_MDDRST);
48 writel(0x00000001, ssif_base + UMC_SIORST);
49 writel(0x00000001, ssif_base + UMC_GIORST);
50 writel(0x00000001, ssif_base + UMC_HD2RST);
51 writel(0x00000001, ssif_base + UMC_VIORST);
52 writel(0x00000001, ssif_base + UMC_DVCRST);
53 writel(0x00000001, ssif_base + UMC_RGLRST);
54 writel(0x00000001, ssif_base + UMC_VPERST);
55 writel(0x00000001, ssif_base + UMC_AIORST);
56 writel(0x00000001, ssif_base + UMC_DMDRST);
59 static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
62 writel(0x66bb0f17, dramcont + UMC_CMDCTLA);
63 writel(0x18c6aa44, dramcont + UMC_CMDCTLB);
64 writel(0x5101387f, dramcont + UMC_INITCTLA);
65 writel(0x43030d3f, dramcont + UMC_INITCTLB);
66 writel(0x00ff00ff, dramcont + UMC_INITCTLC);
67 writel(0x00000d71, dramcont + UMC_DRMMR0);
68 writel(0x00000006, dramcont + UMC_DRMMR1);
69 writel(0x00000298, dramcont + UMC_DRMMR2);
70 writel(0x00000000, dramcont + UMC_DRMMR3);
71 writel(0x003f0617, dramcont + UMC_SPCCTLA);
72 writel(0x00ff0008, dramcont + UMC_SPCCTLB);
73 writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
74 writel(0x000c00ae, dramcont + UMC_RDATACTL_D1);
75 writel(0x04060802, dramcont + UMC_WDATACTL_D0);
76 writel(0x04060802, dramcont + UMC_WDATACTL_D1);
77 writel(0x04a02000, dramcont + UMC_DATASET);
78 writel(0x00000000, ca_base + 0x2300);
79 writel(0x00400020, dramcont + UMC_DCCGCTL);
80 writel(0x0000000f, dramcont + 0x7000);
81 writel(0x0000000f, dramcont + 0x8000);
82 writel(0x000000c3, dramcont + 0x8004);
83 writel(0x00000071, dramcont + 0x8008);
84 writel(0x00000004, dramcont + UMC_FLOWCTLG);
85 writel(0x00000000, dramcont + 0x0060);
86 writel(0x80000201, ca_base + 0xc20);
87 writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
88 writel(0x00200000, dramcont + UMC_FLOWCTLB);
89 writel(0x00004444, dramcont + UMC_FLOWCTLC);
90 writel(0x200a0a00, dramcont + UMC_SPCSETB);
91 writel(0x00010000, dramcont + UMC_SPCSETD);
92 writel(0x80000020, dramcont + UMC_DFICUPDCTLA);
95 static int umc_init_sub(int freq, int size_ch0, int size_ch1)
97 void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
98 void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
99 void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
100 void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
101 void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
102 void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
103 void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1);
104 void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
105 void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1);
107 umc_dram_init_start(dramcont0);
108 umc_dram_init_start(dramcont1);
109 umc_dram_init_poll(dramcont0);
110 umc_dram_init_poll(dramcont1);
112 writel(0x00000101, dramcont0 + UMC_DIOCTLA);
114 ph1_pro4_ddrphy_init(phy0_0, freq, size_ch0);
116 ddrphy_prepare_training(phy0_0, 0);
117 ddrphy_training(phy0_0);
119 writel(0x00000103, dramcont0 + UMC_DIOCTLA);
121 ph1_pro4_ddrphy_init(phy0_1, freq, size_ch0);
123 ddrphy_prepare_training(phy0_1, 1);
124 ddrphy_training(phy0_1);
126 writel(0x00000101, dramcont1 + UMC_DIOCTLA);
128 ph1_pro4_ddrphy_init(phy1_0, freq, size_ch1);
130 ddrphy_prepare_training(phy1_0, 0);
131 ddrphy_training(phy1_0);
133 writel(0x00000103, dramcont1 + UMC_DIOCTLA);
135 ph1_pro4_ddrphy_init(phy1_1, freq, size_ch1);
137 ddrphy_prepare_training(phy1_1, 1);
138 ddrphy_training(phy1_1);
140 umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
141 umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
143 umc_start_ssif(ssif_base);
148 int ph1_pro4_umc_init(const struct uniphier_board_data *bd)
150 if (((bd->dram_ch0_size == SZ_512M && bd->dram_ch0_width == 32) ||
151 (bd->dram_ch0_size == SZ_256M && bd->dram_ch0_width == 16)) &&
152 ((bd->dram_ch1_size == SZ_512M && bd->dram_ch1_width == 32) ||
153 (bd->dram_ch1_size == SZ_256M && bd->dram_ch1_width == 16)) &&
154 bd->dram_freq == 1600) {
155 return umc_init_sub(bd->dram_freq,
156 bd->dram_ch0_size / SZ_128M,
157 bd->dram_ch1_size / SZ_128M);
159 pr_err("Unsupported DDR configuration\n");