git.sur5r.net Git - u-boot/blob - arch/arm/mach-uniphier/dram/umc-ph1-pro4.c

   1 /*
   2  * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <linux/err.h>
   9 #include <linux/io.h>
  10 #include <linux/sizes.h>
  11
  12 #include "../init.h"
  13 #include "ddrphy-regs.h"
  14 #include "umc-regs.h"
  15
  16 #define DRAM_CH_NR      2
  17
  18 enum dram_size {
  19         DRAM_SZ_128M,
  20         DRAM_SZ_256M,
  21         DRAM_SZ_512M,
  22         DRAM_SZ_NR,
  23 };
  24
  25 static u32 umc_spcctla[DRAM_SZ_NR] = {0x002b0617, 0x003f0617, 0x00770617};
  26
  27 static void umc_start_ssif(void __iomem *ssif_base)
  28 {
  29         writel(0x00000000, ssif_base + 0x0000b004);
  30         writel(0xffffffff, ssif_base + 0x0000c004);
  31         writel(0x000fffcf, ssif_base + 0x0000c008);
  32         writel(0x00000001, ssif_base + 0x0000b000);
  33         writel(0x00000001, ssif_base + 0x0000c000);
  34
  35         writel(0x03010100, ssif_base + UMC_HDMCHSEL);
  36         writel(0x03010101, ssif_base + UMC_MDMCHSEL);
  37         writel(0x03010100, ssif_base + UMC_DVCCHSEL);
  38         writel(0x03010100, ssif_base + UMC_DMDCHSEL);
  39
  40         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
  41         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
  42         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
  43         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
  44         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
  45         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
  46         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
  47         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
  48         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
  49         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
  50         writel(0x00000000, ssif_base + 0x0000c044);             /* DCGIV_SSIF_REG */
  51
  52         writel(0x00000001, ssif_base + UMC_CPURST);
  53         writel(0x00000001, ssif_base + UMC_IDSRST);
  54         writel(0x00000001, ssif_base + UMC_IXMRST);
  55         writel(0x00000001, ssif_base + UMC_HDMRST);
  56         writel(0x00000001, ssif_base + UMC_MDMRST);
  57         writel(0x00000001, ssif_base + UMC_HDDRST);
  58         writel(0x00000001, ssif_base + UMC_MDDRST);
  59         writel(0x00000001, ssif_base + UMC_SIORST);
  60         writel(0x00000001, ssif_base + UMC_GIORST);
  61         writel(0x00000001, ssif_base + UMC_HD2RST);
  62         writel(0x00000001, ssif_base + UMC_VIORST);
  63         writel(0x00000001, ssif_base + UMC_DVCRST);
  64         writel(0x00000001, ssif_base + UMC_RGLRST);
  65         writel(0x00000001, ssif_base + UMC_VPERST);
  66         writel(0x00000001, ssif_base + UMC_AIORST);
  67         writel(0x00000001, ssif_base + UMC_DMDRST);
  68 }
  69
  70 static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
  71                              int freq, unsigned long size, bool ddr3plus)
  72 {
  73         enum dram_size dram_size;
  74
  75         if (freq != 1600) {
  76                 pr_err("Unsupported DDR frequency %d MHz\n", freq);
  77                 return -EINVAL;
  78         }
  79
  80         if (ddr3plus) {
  81                 pr_err("DDR3+ is not supported\n");
  82                 return -EINVAL;
  83         }
  84
  85         switch (size) {
  86         case SZ_128M:
  87                 dram_size = DRAM_SZ_128M;
  88                 break;
  89         case SZ_256M:
  90                 dram_size = DRAM_SZ_256M;
  91                 break;
  92         case SZ_512M:
  93                 dram_size = DRAM_SZ_512M;
  94                 break;
  95         default:
  96                 pr_err("unsupported DRAM size 0x%08lx (per 16bit)\n", size);
  97                 return -EINVAL;
  98         }
  99
 100         writel(0x66bb0f17, dramcont + UMC_CMDCTLA);
 101         writel(0x18c6aa44, dramcont + UMC_CMDCTLB);
 102         writel(umc_spcctla[dram_size], dramcont + UMC_SPCCTLA);
 103         writel(0x00ff0008, dramcont + UMC_SPCCTLB);
 104         writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
 105         writel(0x000c00ae, dramcont + UMC_RDATACTL_D1);
 106         writel(0x04060802, dramcont + UMC_WDATACTL_D0);
 107         writel(0x04060802, dramcont + UMC_WDATACTL_D1);
 108         writel(0x04a02000, dramcont + UMC_DATASET);
 109         writel(0x00000000, ca_base + 0x2300);
 110         writel(0x00400020, dramcont + UMC_DCCGCTL);
 111         writel(0x0000000f, dramcont + 0x7000);
 112         writel(0x0000000f, dramcont + 0x8000);
 113         writel(0x000000c3, dramcont + 0x8004);
 114         writel(0x00000071, dramcont + 0x8008);
 115         writel(0x00000004, dramcont + UMC_FLOWCTLG);
 116         writel(0x00000000, dramcont + 0x0060);
 117         writel(0x80000201, ca_base + 0xc20);
 118         writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
 119         writel(0x00200000, dramcont + UMC_FLOWCTLB);
 120         writel(0x00004444, dramcont + UMC_FLOWCTLC);
 121         writel(0x200a0a00, dramcont + UMC_SPCSETB);
 122         writel(0x00010000, dramcont + UMC_SPCSETD);
 123         writel(0x80000020, dramcont + UMC_DFICUPDCTLA);
 124
 125         return 0;
 126 }
 127
 128 static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
 129                        int freq, unsigned long size, unsigned int width,
 130                        bool ddr3plus)
 131 {
 132         void __iomem *phy_base = dc_base + 0x00001000;
 133         int nr_phy = width / 16;
 134         int phy, ret;
 135
 136         umc_dram_init_start(dc_base);
 137         umc_dram_init_poll(dc_base);
 138
 139         for (phy = 0; phy < nr_phy; phy++) {
 140                 writel(0x00000100 | ((1 << (phy + 1)) - 1),
 141                        dc_base + UMC_DIOCTLA);
 142
 143                 ret = ph1_ld4_ddrphy_init(phy_base, freq, ddr3plus);
 144                 if (ret)
 145                         return ret;
 146
 147                 ddrphy_prepare_training(phy_base, phy);
 148                 ret = ddrphy_training(phy_base);
 149                 if (ret)
 150                         return ret;
 151
 152                 phy_base += 0x00001000;
 153         }
 154
 155         return umc_dramcont_init(dc_base, ca_base, freq, size / (width / 16),
 156                                  ddr3plus);
 157 }
 158
 159 int ph1_pro4_umc_init(const struct uniphier_board_data *bd)
 160 {
 161         void __iomem *umc_base = (void __iomem *)0x5b800000;
 162         void __iomem *ca_base = umc_base + 0x00001000;
 163         void __iomem *dc_base = umc_base + 0x00400000;
 164         void __iomem *ssif_base = umc_base;
 165         int ch, ret;
 166
 167         for (ch = 0; ch < DRAM_CH_NR; ch++) {
 168                 ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
 169                                   bd->dram_ch[ch].size,
 170                                   bd->dram_ch[ch].width,
 171                                   bd->dram_ddr3plus);
 172                 if (ret) {
 173                         pr_err("failed to initialize UMC ch%d\n", ch);
 174                         return ret;
 175                 }
 176
 177                 ca_base += 0x00001000;
 178                 dc_base += 0x00200000;
 179         }
 180
 181         umc_start_ssif(ssif_base);
 182
 183         return 0;
 184 }