git.sur5r.net Git - u-boot/blob - arch/arm/mach-uniphier/dram/umc-ph1-sld8.c

   1 /*
   2  * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <linux/err.h>
   9 #include <linux/io.h>
  10 #include <linux/sizes.h>
  11
  12 #include "../init.h"
  13 #include "ddrphy-regs.h"
  14 #include "umc-regs.h"
  15
  16 #define DRAM_CH_NR      2
  17
  18 enum dram_freq {
  19         DRAM_FREQ_1333M,
  20         DRAM_FREQ_1600M,
  21         DRAM_FREQ_NR,
  22 };
  23
  24 enum dram_size {
  25         DRAM_SZ_128M,
  26         DRAM_SZ_256M,
  27         DRAM_SZ_512M,
  28         DRAM_SZ_NR,
  29 };
  30
  31 static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x55990b11, 0x66bb0f17};
  32 static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x46bb0f17};
  33 static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x16958944, 0x18c6ab44};
  34 static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6ab24};
  35 static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
  36         {0x00240512, 0x00350512, 0x00000000}, /* no data for 1333MHz,128MB */
  37         {0x002b0617, 0x003f0617, 0x00670617},
  38 };
  39 static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008};
  40 static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ac};
  41
  42 static int umc_get_rank(int ch)
  43 {
  44         return ch;      /* ch0: rank0, ch1: rank1 for this SoC */
  45 }
  46
  47 static void umc_start_ssif(void __iomem *ssif_base)
  48 {
  49         writel(0x00000000, ssif_base + 0x0000b004);
  50         writel(0xffffffff, ssif_base + 0x0000c004);
  51         writel(0x000fffcf, ssif_base + 0x0000c008);
  52         writel(0x00000001, ssif_base + 0x0000b000);
  53         writel(0x00000001, ssif_base + 0x0000c000);
  54         writel(0x03010101, ssif_base + UMC_MDMCHSEL);
  55         writel(0x03010100, ssif_base + UMC_DMDCHSEL);
  56
  57         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
  58         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
  59         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
  60         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
  61         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
  62         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
  63         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
  64         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
  65         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
  66         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
  67
  68         writel(0x00000001, ssif_base + UMC_CPURST);
  69         writel(0x00000001, ssif_base + UMC_IDSRST);
  70         writel(0x00000001, ssif_base + UMC_IXMRST);
  71         writel(0x00000001, ssif_base + UMC_MDMRST);
  72         writel(0x00000001, ssif_base + UMC_MDDRST);
  73         writel(0x00000001, ssif_base + UMC_SIORST);
  74         writel(0x00000001, ssif_base + UMC_VIORST);
  75         writel(0x00000001, ssif_base + UMC_FRCRST);
  76         writel(0x00000001, ssif_base + UMC_RGLRST);
  77         writel(0x00000001, ssif_base + UMC_AIORST);
  78         writel(0x00000001, ssif_base + UMC_DMDRST);
  79 }
  80
  81 static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
  82                              int freq, unsigned long size, bool ddr3plus)
  83 {
  84         enum dram_freq freq_e;
  85         enum dram_size size_e;
  86
  87         switch (freq) {
  88         case 1333:
  89                 freq_e = DRAM_FREQ_1333M;
  90                 break;
  91         case 1600:
  92                 freq_e = DRAM_FREQ_1600M;
  93                 break;
  94         default:
  95                 pr_err("unsupported DRAM frequency %d MHz\n", freq);
  96                 return -EINVAL;
  97         }
  98
  99         switch (size) {
 100         case 0:
 101                 return 0;
 102         case SZ_128M:
 103                 size_e = DRAM_SZ_128M;
 104                 break;
 105         case SZ_256M:
 106                 size_e = DRAM_SZ_256M;
 107                 break;
 108         case SZ_512M:
 109                 size_e = DRAM_SZ_512M;
 110                 break;
 111         default:
 112                 pr_err("unsupported DRAM size 0x%08lx\n", size);
 113                 return -EINVAL;
 114         }
 115
 116         writel((ddr3plus ? umc_cmdctla_plus : umc_cmdctla)[freq_e],
 117                dramcont + UMC_CMDCTLA);
 118         writel((ddr3plus ? umc_cmdctlb_plus : umc_cmdctlb)[freq_e],
 119                dramcont + UMC_CMDCTLB);
 120         writel(umc_spcctla[freq_e][size_e], dramcont + UMC_SPCCTLA);
 121         writel(umc_spcctlb[freq_e], dramcont + UMC_SPCCTLB);
 122         writel(umc_rdatactl[freq_e], dramcont + UMC_RDATACTL_D0);
 123         writel(0x04060806, dramcont + UMC_WDATACTL_D0);
 124         writel(0x04a02000, dramcont + UMC_DATASET);
 125         writel(0x00000000, ca_base + 0x2300);
 126         writel(0x00400020, dramcont + UMC_DCCGCTL);
 127         writel(0x00000003, dramcont + 0x7000);
 128         writel(0x0000004f, dramcont + 0x8000);
 129         writel(0x000000c3, dramcont + 0x8004);
 130         writel(0x00000077, dramcont + 0x8008);
 131         writel(0x0000003b, dramcont + UMC_DICGCTLA);
 132         writel(0x020a0808, dramcont + UMC_DICGCTLB);
 133         writel(0x00000004, dramcont + UMC_FLOWCTLG);
 134         writel(0x80000201, ca_base + 0xc20);
 135         writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
 136         writel(0x00200000, dramcont + UMC_FLOWCTLB);
 137         writel(0x00004444, dramcont + UMC_FLOWCTLC);
 138         writel(0x200a0a00, dramcont + UMC_SPCSETB);
 139         writel(0x00000000, dramcont + UMC_SPCSETD);
 140         writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
 141
 142         return 0;
 143 }
 144
 145 static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
 146                        int freq, unsigned long size, bool ddr3plus, int ch)
 147 {
 148         void __iomem *phy_base = dc_base + 0x00001000;
 149         int ret;
 150
 151         umc_dram_init_start(dc_base);
 152         umc_dram_init_poll(dc_base);
 153
 154         writel(0x00000101, dc_base + UMC_DIOCTLA);
 155
 156         ret = ph1_ld4_ddrphy_init(phy_base, freq, ddr3plus);
 157         if (ret)
 158                 return ret;
 159
 160         ddrphy_prepare_training(phy_base, umc_get_rank(ch));
 161         ret = ddrphy_training(phy_base);
 162         if (ret)
 163                 return ret;
 164
 165         return umc_dramcont_init(dc_base, ca_base, freq, size, ddr3plus);
 166 }
 167
 168 int ph1_sld8_umc_init(const struct uniphier_board_data *bd)
 169 {
 170         void __iomem *umc_base = (void __iomem *)0x5b800000;
 171         void __iomem *ca_base = umc_base + 0x00001000;
 172         void __iomem *dc_base = umc_base + 0x00400000;
 173         void __iomem *ssif_base = umc_base;
 174         int ch, ret;
 175
 176         for (ch = 0; ch < DRAM_CH_NR; ch++) {
 177                 ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
 178                                   bd->dram_ch[ch].size,
 179                                   bd->dram_ddr3plus, ch);
 180                 if (ret) {
 181                         pr_err("failed to initialize UMC ch%d\n", ch);
 182                         return ret;
 183                 }
 184
 185                 ca_base += 0x00001000;
 186                 dc_base += 0x00200000;
 187         }
 188
 189         umc_start_ssif(ssif_base);
 190
 191         return 0;
 192 }