git.sur5r.net Git - u-boot/blob - arch/arm/mach-uniphier/dram/umc-ph1-sld8.c

   1 /*
   2  * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <linux/err.h>
   9 #include <linux/io.h>
  10 #include <linux/sizes.h>
  11
  12 #include "../init.h"
  13 #include "ddrphy-regs.h"
  14 #include "umc-regs.h"
  15
  16 enum dram_freq {
  17         DRAM_FREQ_1333M,
  18         DRAM_FREQ_1600M,
  19         DRAM_FREQ_NR,
  20 };
  21
  22 enum dram_size {
  23         DRAM_SZ_128M,
  24         DRAM_SZ_256M,
  25         DRAM_SZ_512M,
  26         DRAM_SZ_NR,
  27 };
  28
  29 static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x55990b11, 0x66bb0f17};
  30 static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x46bb0f17};
  31 static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x16958944, 0x18c6ab44};
  32 static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6ab24};
  33 static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
  34         {0x00240512, 0x00350512, 0x00000000}, /* no data for 1333MHz,128MB */
  35         {0x002b0617, 0x003f0617, 0x00670617},
  36 };
  37 static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008};
  38 static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ac};
  39
  40 static void umc_start_ssif(void __iomem *ssif_base)
  41 {
  42         writel(0x00000000, ssif_base + 0x0000b004);
  43         writel(0xffffffff, ssif_base + 0x0000c004);
  44         writel(0x000fffcf, ssif_base + 0x0000c008);
  45         writel(0x00000001, ssif_base + 0x0000b000);
  46         writel(0x00000001, ssif_base + 0x0000c000);
  47         writel(0x03010101, ssif_base + UMC_MDMCHSEL);
  48         writel(0x03010100, ssif_base + UMC_DMDCHSEL);
  49
  50         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
  51         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
  52         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
  53         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
  54         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
  55         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
  56         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
  57         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
  58         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
  59         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
  60
  61         writel(0x00000001, ssif_base + UMC_CPURST);
  62         writel(0x00000001, ssif_base + UMC_IDSRST);
  63         writel(0x00000001, ssif_base + UMC_IXMRST);
  64         writel(0x00000001, ssif_base + UMC_MDMRST);
  65         writel(0x00000001, ssif_base + UMC_MDDRST);
  66         writel(0x00000001, ssif_base + UMC_SIORST);
  67         writel(0x00000001, ssif_base + UMC_VIORST);
  68         writel(0x00000001, ssif_base + UMC_FRCRST);
  69         writel(0x00000001, ssif_base + UMC_RGLRST);
  70         writel(0x00000001, ssif_base + UMC_AIORST);
  71         writel(0x00000001, ssif_base + UMC_DMDRST);
  72 }
  73
  74 static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
  75                              int size, int freq, bool ddr3plus)
  76 {
  77         enum dram_freq freq_e;
  78         enum dram_size size_e;
  79
  80         switch (freq) {
  81         case 1333:
  82                 freq_e = DRAM_FREQ_1333M;
  83                 break;
  84         case 1600:
  85                 freq_e = DRAM_FREQ_1600M;
  86                 break;
  87         default:
  88                 pr_err("unsupported DRAM frequency %d MHz\n", freq);
  89                 return -EINVAL;
  90         }
  91
  92         switch (size) {
  93         case 0:
  94                 return 0;
  95         case 1:
  96                 size_e = DRAM_SZ_128M;
  97                 break;
  98         case 2:
  99                 size_e = DRAM_SZ_256M;
 100                 break;
 101         case 4:
 102                 size_e = DRAM_SZ_512M;
 103                 break;
 104         default:
 105                 pr_err("unsupported DRAM size\n");
 106                 return -EINVAL;
 107         }
 108
 109         writel((ddr3plus ? umc_cmdctla_plus : umc_cmdctla)[freq_e],
 110                dramcont + UMC_CMDCTLA);
 111         writel((ddr3plus ? umc_cmdctlb_plus : umc_cmdctlb)[freq_e],
 112                dramcont + UMC_CMDCTLB);
 113         writel(umc_spcctla[freq_e][size_e], dramcont + UMC_SPCCTLA);
 114         writel(umc_spcctlb[freq_e], dramcont + UMC_SPCCTLB);
 115         writel(umc_rdatactl[freq_e], dramcont + UMC_RDATACTL_D0);
 116         writel(0x04060806, dramcont + UMC_WDATACTL_D0);
 117         writel(0x04a02000, dramcont + UMC_DATASET);
 118         writel(0x00000000, ca_base + 0x2300);
 119         writel(0x00400020, dramcont + UMC_DCCGCTL);
 120         writel(0x00000003, dramcont + 0x7000);
 121         writel(0x0000004f, dramcont + 0x8000);
 122         writel(0x000000c3, dramcont + 0x8004);
 123         writel(0x00000077, dramcont + 0x8008);
 124         writel(0x0000003b, dramcont + UMC_DICGCTLA);
 125         writel(0x020a0808, dramcont + UMC_DICGCTLB);
 126         writel(0x00000004, dramcont + UMC_FLOWCTLG);
 127         writel(0x80000201, ca_base + 0xc20);
 128         writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
 129         writel(0x00200000, dramcont + UMC_FLOWCTLB);
 130         writel(0x00004444, dramcont + UMC_FLOWCTLC);
 131         writel(0x200a0a00, dramcont + UMC_SPCSETB);
 132         writel(0x00000000, dramcont + UMC_SPCSETD);
 133         writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
 134
 135         return 0;
 136 }
 137
 138 static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus)
 139 {
 140         void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
 141         void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
 142         void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
 143         void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
 144         void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
 145         void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
 146         void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
 147
 148         umc_dram_init_start(dramcont0);
 149         umc_dram_init_start(dramcont1);
 150         umc_dram_init_poll(dramcont0);
 151         umc_dram_init_poll(dramcont1);
 152
 153         writel(0x00000101, dramcont0 + UMC_DIOCTLA);
 154
 155         ph1_ld4_ddrphy_init(phy0_0, freq, ddr3plus);
 156
 157         ddrphy_prepare_training(phy0_0, 0);
 158         ddrphy_training(phy0_0);
 159
 160         writel(0x00000101, dramcont1 + UMC_DIOCTLA);
 161
 162         ph1_ld4_ddrphy_init(phy1_0, freq, ddr3plus);
 163
 164         ddrphy_prepare_training(phy1_0, 1);
 165         ddrphy_training(phy1_0);
 166
 167         umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq, ddr3plus);
 168         umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq, ddr3plus);
 169
 170         umc_start_ssif(ssif_base);
 171
 172         return 0;
 173 }
 174
 175 int ph1_sld8_umc_init(const struct uniphier_board_data *bd)
 176 {
 177         if ((bd->dram_ch[0].size == SZ_128M || bd->dram_ch[0].size == SZ_256M) &&
 178             (bd->dram_ch[1].size == SZ_128M || bd->dram_ch[1].size == SZ_256M) &&
 179             bd->dram_freq == 1333 &&
 180             bd->dram_ch[0].width == 16 && bd->dram_ch[1].width == 16) {
 181                 return umc_init_sub(bd->dram_freq,
 182                                     bd->dram_ch[0].size / SZ_128M,
 183                                     bd->dram_ch[1].size / SZ_128M,
 184                                     bd->dram_ddr3plus);
 185         } else {
 186                 pr_err("Unsupported DDR configuration\n");
 187                 return -EINVAL;
 188         }
 189 }