2 * Copyright (C) 2011-2014 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/err.h>
12 #include <linux/sizes.h>
13 #include <asm/processor.h>
16 #include "ddrphy-init.h"
28 static u32 umc_spcctla[DRAM_SZ_NR] = {0x002b0617, 0x003f0617, 0x00770617};
30 static void umc_start_ssif(void __iomem *ssif_base)
32 writel(0x00000000, ssif_base + 0x0000b004);
33 writel(0xffffffff, ssif_base + 0x0000c004);
34 writel(0x000fffcf, ssif_base + 0x0000c008);
35 writel(0x00000001, ssif_base + 0x0000b000);
36 writel(0x00000001, ssif_base + 0x0000c000);
38 writel(0x03010100, ssif_base + UMC_HDMCHSEL);
39 writel(0x03010101, ssif_base + UMC_MDMCHSEL);
40 writel(0x03010100, ssif_base + UMC_DVCCHSEL);
41 writel(0x03010100, ssif_base + UMC_DMDCHSEL);
43 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
44 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
45 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
46 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
47 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
48 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
49 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
50 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
51 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
52 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
53 writel(0x00000000, ssif_base + 0x0000c044); /* DCGIV_SSIF_REG */
55 writel(0x00000001, ssif_base + UMC_CPURST);
56 writel(0x00000001, ssif_base + UMC_IDSRST);
57 writel(0x00000001, ssif_base + UMC_IXMRST);
58 writel(0x00000001, ssif_base + UMC_HDMRST);
59 writel(0x00000001, ssif_base + UMC_MDMRST);
60 writel(0x00000001, ssif_base + UMC_HDDRST);
61 writel(0x00000001, ssif_base + UMC_MDDRST);
62 writel(0x00000001, ssif_base + UMC_SIORST);
63 writel(0x00000001, ssif_base + UMC_GIORST);
64 writel(0x00000001, ssif_base + UMC_HD2RST);
65 writel(0x00000001, ssif_base + UMC_VIORST);
66 writel(0x00000001, ssif_base + UMC_DVCRST);
67 writel(0x00000001, ssif_base + UMC_RGLRST);
68 writel(0x00000001, ssif_base + UMC_VPERST);
69 writel(0x00000001, ssif_base + UMC_AIORST);
70 writel(0x00000001, ssif_base + UMC_DMDRST);
73 static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base,
74 int freq, unsigned long size, bool ddr3plus)
76 enum dram_size size_e;
79 pr_err("Unsupported DDR frequency %d MHz\n", freq);
84 pr_err("DDR3+ is not supported\n");
90 size_e = DRAM_SZ_128M;
93 size_e = DRAM_SZ_256M;
96 size_e = DRAM_SZ_512M;
99 pr_err("unsupported DRAM size 0x%08lx (per 16bit)\n", size);
103 writel(0x66bb0f17, dc_base + UMC_CMDCTLA);
104 writel(0x18c6aa44, dc_base + UMC_CMDCTLB);
105 writel(umc_spcctla[size_e], dc_base + UMC_SPCCTLA);
106 writel(0x00ff0008, dc_base + UMC_SPCCTLB);
107 writel(0x000c00ae, dc_base + UMC_RDATACTL_D0);
108 writel(0x000c00ae, dc_base + UMC_RDATACTL_D1);
109 writel(0x04060802, dc_base + UMC_WDATACTL_D0);
110 writel(0x04060802, dc_base + UMC_WDATACTL_D1);
111 writel(0x04a02000, dc_base + UMC_DATASET);
112 writel(0x00000000, ca_base + 0x2300);
113 writel(0x00400020, dc_base + UMC_DCCGCTL);
114 writel(0x0000000f, dc_base + 0x7000);
115 writel(0x0000000f, dc_base + 0x8000);
116 writel(0x000000c3, dc_base + 0x8004);
117 writel(0x00000071, dc_base + 0x8008);
118 writel(0x00000004, dc_base + UMC_FLOWCTLG);
119 writel(0x00000000, dc_base + 0x0060);
120 writel(0x80000201, ca_base + 0xc20);
121 writel(0x0801e01e, dc_base + UMC_FLOWCTLA);
122 writel(0x00200000, dc_base + UMC_FLOWCTLB);
123 writel(0x00004444, dc_base + UMC_FLOWCTLC);
124 writel(0x200a0a00, dc_base + UMC_SPCSETB);
125 writel(0x00010000, dc_base + UMC_SPCSETD);
126 writel(0x80000020, dc_base + UMC_DFICUPDCTLA);
131 static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
132 int freq, unsigned long size, unsigned int width,
135 void __iomem *phy_base = dc_base + 0x00001000;
136 int nr_phy = width / 16;
139 writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
140 while (readl(dc_base + UMC_INITSTAT) & UMC_INITSTAT_INIT1ST)
143 for (phy = 0; phy < nr_phy; phy++) {
144 writel(0x00000100 | ((1 << (phy + 1)) - 1),
145 dc_base + UMC_DIOCTLA);
147 ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus);
151 ddrphy_prepare_training(phy_base, phy);
152 ret = ddrphy_training(phy_base);
156 phy_base += 0x00001000;
159 return umc_dramcont_init(dc_base, ca_base, freq, size / (width / 16),
163 int uniphier_pro4_umc_init(const struct uniphier_board_data *bd)
165 void __iomem *umc_base = (void __iomem *)0x5b800000;
166 void __iomem *ca_base = umc_base + 0x00001000;
167 void __iomem *dc_base = umc_base + 0x00400000;
168 void __iomem *ssif_base = umc_base;
171 for (ch = 0; ch < DRAM_CH_NR; ch++) {
172 ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
173 bd->dram_ch[ch].size,
174 bd->dram_ch[ch].width,
175 !!(bd->flags & UNIPHIER_BD_DDR3PLUS));
177 pr_err("failed to initialize UMC ch%d\n", ch);
181 ca_base += 0x00001000;
182 dc_base += 0x00200000;
185 umc_start_ssif(ssif_base);