git.sur5r.net Git - u-boot/blob - arch/arm/mach-uniphier/dram/umc-proxstream2.c

   1 /*
   2  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   3  *
   4  * based on commit 21b6e480f92ccc38fe0502e3116411d6509d3bf2 of Diag by:
   5  * Copyright (C) 2015 Socionext Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <linux/err.h>
  12 #include <linux/io.h>
  13 #include <linux/sizes.h>
  14 #include <asm/processor.h>
  15
  16 #include "../init.h"
  17 #include "../soc-info.h"
  18 #include "ddrmphy-regs.h"
  19
  20 /* UM registers */
  21 #define UMC_MBUS0               0x00080004
  22 #define UMC_MBUS1               0x00081004
  23 #define UMC_MBUS2               0x00082004
  24 #define UMC_MBUS3               0x00083004
  25
  26 /* UD registers */
  27 #define UMC_BITPERPIXELMODE_D0  0x010
  28 #define UMC_PAIR1DOFF_D0        0x054
  29
  30 /* DC registers */
  31 #define UMC_INITSET             0x014
  32 #define UMC_INITSTAT            0x018
  33 #define UMC_CMDCTLA             0x000
  34 #define UMC_CMDCTLB             0x004
  35 #define UMC_SPCCTLA             0x030
  36 #define UMC_SPCCTLB             0x034
  37 #define UMC_SPCSETB             0x03c
  38 #define   UMC_SPCSETB_AREFMD_MASK       (0x3)   /* Auto Refresh Mode */
  39 #define   UMC_SPCSETB_AREFMD_ARB        (0x0)   /* control by arbitor */
  40 #define   UMC_SPCSETB_AREFMD_CONT       (0x1)   /* control by DRAMCONT */
  41 #define   UMC_SPCSETB_AREFMD_REG        (0x2)   /* control by register */
  42 #define UMC_ACSSETA             0x060
  43 #define UMC_FLOWCTLA            0x400
  44 #define UMC_FLOWCTLB            0x404
  45 #define UMC_FLOWCTLC            0x408
  46 #define UMC_FLOWCTLG            0x508
  47 #define UMC_FLOWCTLOB0          0x520
  48 #define UMC_FLOWCTLOB1          0x524
  49 #define UMC_RDATACTL_D0         0x600
  50 #define   UMC_RDATACTL_RADLTY_SHIFT     4
  51 #define   UMC_RDATACTL_RADLTY_MASK      (0xf << (UMC_RDATACTL_RADLTY_SHIFT))
  52 #define   UMC_RDATACTL_RAD2LTY_SHIFT    8
  53 #define   UMC_RDATACTL_RAD2LTY_MASK     (0xf << (UMC_RDATACTL_RAD2LTY_SHIFT))
  54 #define UMC_WDATACTL_D0         0x604
  55 #define UMC_RDATACTL_D1         0x608
  56 #define UMC_WDATACTL_D1         0x60c
  57 #define UMC_DATASET             0x610
  58 #define UMC_RESPCTL             0x624
  59 #define UMC_DCCGCTL             0x720
  60 #define UMC_ERRMASKA            0x958
  61 #define UMC_ERRMASKB            0x95c
  62 #define UMC_BSICMAPSET          0x988
  63 #define UMC_DIOCTLA             0xc00
  64 #define   UMC_DIOCTLA_CTL_NRST          BIT(8)  /* ctl_rst_n */
  65 #define   UMC_DIOCTLA_CFG_NRST          BIT(0)  /* cfg_rst_n */
  66 #define UMC_DFICUPDCTLA         0xc20
  67
  68 enum dram_freq {
  69         FREQ_1866M,
  70         FREQ_2133M,
  71         FREQ_NR,
  72 };
  73
  74 enum dram_size {
  75         SIZE_0,
  76         SIZE_512M,
  77         SIZE_1G,
  78         SIZE_NR,
  79 };
  80
  81 static u32 ddrphy_pgcr2[FREQ_NR] = {0x00FC7E5D, 0x00FC90AB};
  82 static u32 ddrphy_ptr0[FREQ_NR] = {0x0EA09205, 0x10C0A6C6};
  83 static u32 ddrphy_ptr1[FREQ_NR] = {0x0DAC041B, 0x0FA104B1};
  84 static u32 ddrphy_ptr3[FREQ_NR] = {0x15171e45, 0x18182357};
  85 static u32 ddrphy_ptr4[FREQ_NR] = {0x0e9ad8e9, 0x10b34157};
  86 static u32 ddrphy_dtpr0[FREQ_NR] = {0x35a00d88, 0x39e40e88};
  87 static u32 ddrphy_dtpr1[FREQ_NR] = {0x2288cc2c, 0x228a04d0};
  88 static u32 ddrphy_dtpr2[FREQ_NR] = {0x50005e00, 0x50006a00};
  89 static u32 ddrphy_dtpr3[FREQ_NR] = {0x0010cb49, 0x0010ec89};
  90 static u32 ddrphy_mr0[FREQ_NR] = {0x00000115, 0x00000125};
  91 static u32 ddrphy_mr2[FREQ_NR] = {0x000002a0, 0x000002a8};
  92
  93 static u32 umc_cmdctla[FREQ_NR] = {0x66DD131D, 0x77EE1722};
  94 /*
  95  * The ch2 is a different generation UMC core.
  96  * The register spec is different, unfortunately.
  97  */
  98 static u32 umc_cmdctlb_ch01[FREQ_NR] = {0x13E87C44, 0x18F88C44};
  99 static u32 umc_cmdctlb_ch2[FREQ_NR] = {0x19E8DC44, 0x1EF8EC44};
 100 static u32 umc_spcctla[FREQ_NR][SIZE_NR] = {
 101         {0x00000000, 0x004A071D, 0x0078071D},
 102         {0x00000000, 0x0055081E, 0x0089081E},
 103 };
 104
 105 static u32 umc_spcctlb[] = {0x00FF000A, 0x00FF000B};
 106 /* The ch2 is different for some reason only hardware guys know... */
 107 static u32 umc_flowctla_ch01[] = {0x0800001E, 0x08000022};
 108 static u32 umc_flowctla_ch2[] = {0x0800001E, 0x0800001E};
 109
 110 /* DDR multiPHY */
 111 static inline int ddrphy_get_rank(int dx)
 112 {
 113         return dx / 2;
 114 }
 115
 116 static void ddrphy_fifo_reset(void __iomem *phy_base)
 117 {
 118         u32 tmp;
 119
 120         tmp = readl(phy_base + DMPHY_PGCR0);
 121         tmp &= ~DMPHY_PGCR0_PHYFRST;
 122         writel(tmp, phy_base + DMPHY_PGCR0);
 123
 124         udelay(1);
 125
 126         tmp |= DMPHY_PGCR0_PHYFRST;
 127         writel(tmp, phy_base + DMPHY_PGCR0);
 128
 129         udelay(1);
 130 }
 131
 132 static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable)
 133 {
 134         u32 tmp;
 135
 136         tmp = readl(phy_base + DMPHY_PGCR1);
 137
 138         if (enable)
 139                 tmp &= ~DMPHY_PGCR1_INHVT;
 140         else
 141                 tmp |= DMPHY_PGCR1_INHVT;
 142
 143         writel(tmp, phy_base + DMPHY_PGCR1);
 144
 145         if (!enable) {
 146                 while (!(readl(phy_base + DMPHY_PGSR1) & DMPHY_PGSR1_VTSTOP))
 147                         cpu_relax();
 148         }
 149 }
 150
 151 static void ddrphy_dqs_delay_fixup(void __iomem *phy_base, int nr_dx, int step)
 152 {
 153         int dx;
 154         u32 lcdlr1, rdqsd;
 155         void __iomem *dx_base = phy_base + DMPHY_DX_BASE;
 156
 157         ddrphy_vt_ctrl(phy_base, 0);
 158
 159         for (dx = 0; dx < nr_dx; dx++) {
 160                 lcdlr1 = readl(dx_base + DMPHY_DX_LCDLR1);
 161                 rdqsd = (lcdlr1 >> 8) & 0xff;
 162                 rdqsd = clamp(rdqsd + step, 0U, 0xffU);
 163                 lcdlr1 = (lcdlr1 & ~(0xff << 8)) | (rdqsd << 8);
 164                 writel(lcdlr1, dx_base + DMPHY_DX_LCDLR1);
 165                 readl(dx_base + DMPHY_DX_LCDLR1); /* relax */
 166                 dx_base += DMPHY_DX_STRIDE;
 167         }
 168
 169         ddrphy_vt_ctrl(phy_base, 1);
 170 }
 171
 172 static int ddrphy_get_system_latency(void __iomem *phy_base, int width)
 173 {
 174         void __iomem *dx_base = phy_base + DMPHY_DX_BASE;
 175         const int nr_dx = width / 8;
 176         int dx, rank;
 177         u32 gtr;
 178         int dgsl, dgsl_min = INT_MAX, dgsl_max = 0;
 179
 180         for (dx = 0; dx < nr_dx; dx++) {
 181                 gtr = readl(dx_base + DMPHY_DX_GTR);
 182                 for (rank = 0; rank < 4; rank++) {
 183                         dgsl = gtr & 0x7;
 184                         /* if dgsl is zero, this rank was not trained. skip. */
 185                         if (dgsl) {
 186                                 dgsl_min = min(dgsl_min, dgsl);
 187                                 dgsl_max = max(dgsl_max, dgsl);
 188                         }
 189                         gtr >>= 3;
 190                 }
 191                 dx_base += DMPHY_DX_STRIDE;
 192         }
 193
 194         if (dgsl_min != dgsl_max)
 195                 printf("DQS Gateing System Latencies are not all leveled.\n");
 196
 197         return dgsl_max;
 198 }
 199
 200 static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width)
 201 {
 202         u32 tmp;
 203         void __iomem *zq_base, *dx_base;
 204         int zq, dx;
 205         int nr_dx;
 206
 207         nr_dx = width / 8;
 208
 209         writel(DMPHY_PIR_ZCALBYP,        phy_base + DMPHY_PIR);
 210         /*
 211          * Disable RGLVT bit (Read DQS Gating LCDL Delay VT Compensation)
 212          * to avoid read error issue.
 213          */
 214         writel(0x07d81e37,         phy_base + DMPHY_PGCR0);
 215         writel(0x0200c4e0,         phy_base + DMPHY_PGCR1);
 216
 217         tmp = ddrphy_pgcr2[freq];
 218         if (width >= 32)
 219                 tmp |= DMPHY_PGCR2_DUALCHN | DMPHY_PGCR2_ACPDDC;
 220         writel(tmp, phy_base + DMPHY_PGCR2);
 221
 222         writel(ddrphy_ptr0[freq],  phy_base + DMPHY_PTR0);
 223         writel(ddrphy_ptr1[freq],  phy_base + DMPHY_PTR1);
 224         writel(0x00083def,         phy_base + DMPHY_PTR2);
 225         writel(ddrphy_ptr3[freq],  phy_base + DMPHY_PTR3);
 226         writel(ddrphy_ptr4[freq],  phy_base + DMPHY_PTR4);
 227
 228         writel(0x55555555, phy_base + DMPHY_ACIOCR1);
 229         writel(0x00000000, phy_base + DMPHY_ACIOCR2);
 230         writel(0x55555555, phy_base + DMPHY_ACIOCR3);
 231         writel(0x00000000, phy_base + DMPHY_ACIOCR4);
 232         writel(0x00000055, phy_base + DMPHY_ACIOCR5);
 233         writel(0x00181aa4, phy_base + DMPHY_DXCCR);
 234
 235         writel(0x0024641e, phy_base + DMPHY_DSGCR);
 236         writel(0x0000040b, phy_base + DMPHY_DCR);
 237         writel(ddrphy_dtpr0[freq], phy_base + DMPHY_DTPR0);
 238         writel(ddrphy_dtpr1[freq], phy_base + DMPHY_DTPR1);
 239         writel(ddrphy_dtpr2[freq], phy_base + DMPHY_DTPR2);
 240         writel(ddrphy_dtpr3[freq], phy_base + DMPHY_DTPR3);
 241         writel(ddrphy_mr0[freq], phy_base + DMPHY_MR0);
 242         writel(0x00000006,       phy_base + DMPHY_MR1);
 243         writel(ddrphy_mr2[freq], phy_base + DMPHY_MR2);
 244         writel(0x00000000,       phy_base + DMPHY_MR3);
 245
 246         tmp = 0;
 247         for (dx = 0; dx < nr_dx; dx++)
 248                 tmp |= BIT(DMPHY_DTCR_RANKEN_SHIFT + ddrphy_get_rank(dx));
 249         writel(0x90003087 | tmp, phy_base + DMPHY_DTCR);
 250
 251         writel(0x00000000, phy_base + DMPHY_DTAR0);
 252         writel(0x00000008, phy_base + DMPHY_DTAR1);
 253         writel(0x00000010, phy_base + DMPHY_DTAR2);
 254         writel(0x00000018, phy_base + DMPHY_DTAR3);
 255         writel(0xdd22ee11, phy_base + DMPHY_DTDR0);
 256         writel(0x7788bb44, phy_base + DMPHY_DTDR1);
 257
 258         /* impedance control settings */
 259         writel(0x04048900, phy_base + DMPHY_ZQCR);
 260
 261         zq_base = phy_base + DMPHY_ZQ_BASE;
 262         for (zq = 0; zq < 4; zq++) {
 263                 /*
 264                  * board-dependent
 265                  * PXS2: CH0ZQ0=0x5B, CH1ZQ0=0x5B, CH2ZQ0=0x59, others=0x5D
 266                  */
 267                 writel(0x0007BB5D, zq_base + DMPHY_ZQ_PR);
 268                 zq_base += DMPHY_ZQ_STRIDE;
 269         }
 270
 271         /* DATX8 settings */
 272         dx_base = phy_base + DMPHY_DX_BASE;
 273         for (dx = 0; dx < 4; dx++) {
 274                 tmp = readl(dx_base + DMPHY_DX_GCR0);
 275                 tmp &= ~DMPHY_DX_GCR0_WLRKEN_MASK;
 276                 tmp |= BIT(DMPHY_DX_GCR0_WLRKEN_SHIFT + ddrphy_get_rank(dx)) &
 277                                                 DMPHY_DX_GCR0_WLRKEN_MASK;
 278                 writel(tmp, dx_base + DMPHY_DX_GCR0);
 279
 280                 writel(0x00000000, dx_base + DMPHY_DX_GCR1);
 281                 writel(0x00000000, dx_base + DMPHY_DX_GCR2);
 282                 writel(0x00000000, dx_base + DMPHY_DX_GCR3);
 283                 dx_base += DMPHY_DX_STRIDE;
 284         }
 285
 286         while (!(readl(phy_base + DMPHY_PGSR0) & DMPHY_PGSR0_IDONE))
 287                 cpu_relax();
 288
 289         ddrphy_dqs_delay_fixup(phy_base, nr_dx, -4);
 290 }
 291
 292 struct ddrphy_init_sequence {
 293         char *description;
 294         u32 init_flag;
 295         u32 done_flag;
 296         u32 err_flag;
 297 };
 298
 299 static const struct ddrphy_init_sequence impedance_calibration_sequence[] = {
 300         {
 301                 "Impedance Calibration",
 302                 DMPHY_PIR_ZCAL,
 303                 DMPHY_PGSR0_ZCDONE,
 304                 DMPHY_PGSR0_ZCERR,
 305         },
 306         { /* sentinel */ }
 307 };
 308
 309 static const struct ddrphy_init_sequence dram_init_sequence[] = {
 310         {
 311                 "DRAM Initialization",
 312                 DMPHY_PIR_DRAMRST | DMPHY_PIR_DRAMINIT,
 313                 DMPHY_PGSR0_DIDONE,
 314                 0,
 315         },
 316         { /* sentinel */ }
 317 };
 318
 319 static const struct ddrphy_init_sequence training_sequence[] = {
 320         {
 321                 "Write Leveling",
 322                 DMPHY_PIR_WL,
 323                 DMPHY_PGSR0_WLDONE,
 324                 DMPHY_PGSR0_WLERR,
 325         },
 326         {
 327                 "Read DQS Gate Training",
 328                 DMPHY_PIR_QSGATE,
 329                 DMPHY_PGSR0_QSGDONE,
 330                 DMPHY_PGSR0_QSGERR,
 331         },
 332         {
 333                 "Write Leveling Adjustment",
 334                 DMPHY_PIR_WLADJ,
 335                 DMPHY_PGSR0_WLADONE,
 336                 DMPHY_PGSR0_WLAERR,
 337         },
 338         {
 339                 "Read Bit Deskew",
 340                 DMPHY_PIR_RDDSKW,
 341                 DMPHY_PGSR0_RDDONE,
 342                 DMPHY_PGSR0_RDERR,
 343         },
 344         {
 345                 "Write Bit Deskew",
 346                 DMPHY_PIR_WRDSKW,
 347                 DMPHY_PGSR0_WDDONE,
 348                 DMPHY_PGSR0_WDERR,
 349         },
 350         {
 351                 "Read Eye Training",
 352                 DMPHY_PIR_RDEYE,
 353                 DMPHY_PGSR0_REDONE,
 354                 DMPHY_PGSR0_REERR,
 355         },
 356         {
 357                 "Write Eye Training",
 358                 DMPHY_PIR_WREYE,
 359                 DMPHY_PGSR0_WEDONE,
 360                 DMPHY_PGSR0_WEERR,
 361         },
 362         { /* sentinel */ }
 363 };
 364
 365 static int __ddrphy_training(void __iomem *phy_base,
 366                              const struct ddrphy_init_sequence *seq)
 367 {
 368         const struct ddrphy_init_sequence *s;
 369         u32 pgsr0;
 370         u32 init_flag = DMPHY_PIR_INIT;
 371         u32 done_flag = DMPHY_PGSR0_IDONE;
 372         int timeout = 50000; /* 50 msec is long enough */
 373 #ifdef DISPLAY_ELAPSED_TIME
 374         ulong start = get_timer(0);
 375 #endif
 376
 377         for (s = seq; s->description; s++) {
 378                 init_flag |= s->init_flag;
 379                 done_flag |= s->done_flag;
 380         }
 381
 382         writel(init_flag, phy_base + DMPHY_PIR);
 383
 384         do {
 385                 if (--timeout < 0) {
 386                         printf("%s: error: timeout during DDR training\n",
 387                                __func__);
 388                         return -ETIMEDOUT;
 389                 }
 390                 udelay(1);
 391                 pgsr0 = readl(phy_base + DMPHY_PGSR0);
 392         } while ((pgsr0 & done_flag) != done_flag);
 393
 394         for (s = seq; s->description; s++) {
 395                 if (pgsr0 & s->err_flag) {
 396                         printf("%s: error: %s failed\n", __func__,
 397                                s->description);
 398                         return -EIO;
 399                 }
 400         }
 401
 402 #ifdef DISPLAY_ELAPSED_TIME
 403         printf("%s: info: elapsed time %ld msec\n", get_timer(start));
 404 #endif
 405
 406         return 0;
 407 }
 408
 409 static int ddrphy_impedance_calibration(void __iomem *phy_base)
 410 {
 411         int ret;
 412         u32 tmp;
 413
 414         ret = __ddrphy_training(phy_base, impedance_calibration_sequence);
 415         if (ret)
 416                 return ret;
 417
 418         /*
 419          * Because of a hardware bug, IDONE flag is set when the first ZQ block
 420          * is calibrated.  The flag does not guarantee the completion for all
 421          * the ZQ blocks.  Wait a little more just in case.
 422          */
 423         udelay(1);
 424
 425         /* reflect ZQ settings and enable average algorithm*/
 426         tmp = readl(phy_base + DMPHY_ZQCR);
 427         tmp |= DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
 428         writel(tmp, phy_base + DMPHY_ZQCR);
 429         tmp &= ~DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
 430         tmp |= DMPHY_ZQCR_AVGEN;
 431         writel(tmp, phy_base + DMPHY_ZQCR);
 432
 433         return 0;
 434 }
 435
 436 static int ddrphy_dram_init(void __iomem *phy_base)
 437 {
 438         return __ddrphy_training(phy_base, dram_init_sequence);
 439 }
 440
 441 static int ddrphy_training(void __iomem *phy_base)
 442 {
 443         return __ddrphy_training(phy_base, training_sequence);
 444 }
 445
 446 /* UMC */
 447 static void umc_set_system_latency(void __iomem *umc_dc_base, int phy_latency)
 448 {
 449         u32 val;
 450         int latency;
 451
 452         val = readl(umc_dc_base + UMC_RDATACTL_D0);
 453         latency = (val & UMC_RDATACTL_RADLTY_MASK) >> UMC_RDATACTL_RADLTY_SHIFT;
 454         latency += (val & UMC_RDATACTL_RAD2LTY_MASK) >>
 455                                                 UMC_RDATACTL_RAD2LTY_SHIFT;
 456         /*
 457          * UMC works at the half clock rate of the PHY.
 458          * The LSB of latency is ignored
 459          */
 460         latency += phy_latency & ~1;
 461
 462         val &= ~(UMC_RDATACTL_RADLTY_MASK | UMC_RDATACTL_RAD2LTY_MASK);
 463         if (latency > 0xf) {
 464                 val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT;
 465                 val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT;
 466         } else {
 467                 val |= latency << UMC_RDATACTL_RADLTY_SHIFT;
 468         }
 469
 470         writel(val, umc_dc_base + UMC_RDATACTL_D0);
 471         writel(val, umc_dc_base + UMC_RDATACTL_D1);
 472
 473         readl(umc_dc_base + UMC_RDATACTL_D1); /* relax */
 474 }
 475
 476 /* enable/disable auto refresh */
 477 void umc_refresh_ctrl(void __iomem *umc_dc_base, int enable)
 478 {
 479         u32 tmp;
 480
 481         tmp = readl(umc_dc_base + UMC_SPCSETB);
 482         tmp &= ~UMC_SPCSETB_AREFMD_MASK;
 483
 484         if (enable)
 485                 tmp |= UMC_SPCSETB_AREFMD_ARB;
 486         else
 487                 tmp |= UMC_SPCSETB_AREFMD_REG;
 488
 489         writel(tmp, umc_dc_base + UMC_SPCSETB);
 490         udelay(1);
 491 }
 492
 493 static void umc_ud_init(void __iomem *umc_base, int ch)
 494 {
 495         writel(0x00000003, umc_base + UMC_BITPERPIXELMODE_D0);
 496
 497         if (ch == 2)
 498                 writel(0x00000033, umc_base + UMC_PAIR1DOFF_D0);
 499 }
 500
 501 static void umc_dc_init(void __iomem *umc_dc_base, enum dram_freq freq,
 502                         enum dram_size size, int ch, int width)
 503 {
 504         int latency;
 505         u32 val;
 506
 507         writel(umc_cmdctla[freq], umc_dc_base + UMC_CMDCTLA);
 508
 509         writel(ch == 2 ? umc_cmdctlb_ch2[freq] : umc_cmdctlb_ch01[freq],
 510                umc_dc_base + UMC_CMDCTLB);
 511
 512         writel(umc_spcctla[freq][size / (width / 16)],
 513                umc_dc_base + UMC_SPCCTLA);
 514         writel(umc_spcctlb[freq], umc_dc_base + UMC_SPCCTLB);
 515
 516         val = 0x000e000e;
 517         latency = 12;
 518         /* ES2 inserted one more FF to the logic. */
 519         if (uniphier_get_soc_model() >= 2)
 520                 latency += 2;
 521
 522         if (latency > 0xf) {
 523                 val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT;
 524                 val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT;
 525         } else {
 526                 val |= latency << UMC_RDATACTL_RADLTY_SHIFT;
 527         }
 528
 529         writel(val, umc_dc_base + UMC_RDATACTL_D0);
 530         if (width >= 32)
 531                 writel(val, umc_dc_base + UMC_RDATACTL_D1);
 532
 533         writel(0x04060A02, umc_dc_base + UMC_WDATACTL_D0);
 534         if (width >= 32)
 535                 writel(0x04060A02, umc_dc_base + UMC_WDATACTL_D1);
 536         writel(0x04000000, umc_dc_base + UMC_DATASET);
 537         writel(0x00400020, umc_dc_base + UMC_DCCGCTL);
 538         writel(0x00000084, umc_dc_base + UMC_FLOWCTLG);
 539         writel(0x00000000, umc_dc_base + UMC_ACSSETA);
 540
 541         writel(ch == 2 ? umc_flowctla_ch2[freq] : umc_flowctla_ch01[freq],
 542                umc_dc_base + UMC_FLOWCTLA);
 543
 544         writel(0x00004400, umc_dc_base + UMC_FLOWCTLC);
 545         writel(0x200A0A00, umc_dc_base + UMC_SPCSETB);
 546         writel(0x00000520, umc_dc_base + UMC_DFICUPDCTLA);
 547         writel(0x0000000D, umc_dc_base + UMC_RESPCTL);
 548
 549         if (ch != 2) {
 550                 writel(0x00202000, umc_dc_base + UMC_FLOWCTLB);
 551                 writel(0xFDBFFFFF, umc_dc_base + UMC_FLOWCTLOB0);
 552                 writel(0xFFFFFFFF, umc_dc_base + UMC_FLOWCTLOB1);
 553                 writel(0x00080700, umc_dc_base + UMC_BSICMAPSET);
 554         } else {
 555                 writel(0x00200000, umc_dc_base + UMC_FLOWCTLB);
 556                 writel(0x00000000, umc_dc_base + UMC_BSICMAPSET);
 557         }
 558
 559         writel(0x00000000, umc_dc_base + UMC_ERRMASKA);
 560         writel(0x00000000, umc_dc_base + UMC_ERRMASKB);
 561 }
 562
 563 static int umc_init(void __iomem *umc_base, enum dram_freq freq, int ch,
 564                     enum dram_size size, int width)
 565 {
 566         void __iomem *umc_dc_base = umc_base + 0x00011000;
 567         void __iomem *phy_base = umc_base + 0x00030000;
 568         int ret;
 569
 570         writel(0x00000002, umc_dc_base + UMC_INITSET);
 571         while (readl(umc_dc_base + UMC_INITSTAT) & BIT(2))
 572                 cpu_relax();
 573
 574         /* deassert PHY reset signals */
 575         writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST,
 576                umc_dc_base + UMC_DIOCTLA);
 577
 578         ddrphy_init(phy_base, freq, width);
 579
 580         ret = ddrphy_impedance_calibration(phy_base);
 581         if (ret)
 582                 return ret;
 583
 584         ddrphy_dram_init(phy_base);
 585         if (ret)
 586                 return ret;
 587
 588         umc_dc_init(umc_dc_base, freq, size, ch, width);
 589
 590         umc_ud_init(umc_base, ch);
 591
 592         if (size) {
 593                 ret = ddrphy_training(phy_base);
 594                 if (ret)
 595                         return ret;
 596         }
 597
 598         udelay(1);
 599
 600         /* match the system latency between UMC and PHY */
 601         umc_set_system_latency(umc_dc_base,
 602                                ddrphy_get_system_latency(phy_base, width));
 603
 604         udelay(1);
 605
 606         /* stop auto refresh before clearing FIFO in PHY */
 607         umc_refresh_ctrl(umc_dc_base, 0);
 608         ddrphy_fifo_reset(phy_base);
 609         umc_refresh_ctrl(umc_dc_base, 1);
 610
 611         udelay(10);
 612
 613         return 0;
 614 }
 615
 616 static void um_init(void __iomem *um_base)
 617 {
 618         writel(0x000000ff, um_base + UMC_MBUS0);
 619         writel(0x000000ff, um_base + UMC_MBUS1);
 620         writel(0x000000ff, um_base + UMC_MBUS2);
 621         writel(0x000000ff, um_base + UMC_MBUS3);
 622 }
 623
 624 int proxstream2_umc_init(const struct uniphier_board_data *bd)
 625 {
 626         void __iomem *um_base = (void __iomem *)0x5b600000;
 627         void __iomem *umc_ch0_base = (void __iomem *)0x5b800000;
 628         void __iomem *umc_ch1_base = (void __iomem *)0x5ba00000;
 629         void __iomem *umc_ch2_base = (void __iomem *)0x5bc00000;
 630         enum dram_freq freq;
 631         int ret;
 632
 633         switch (bd->dram_freq) {
 634         case 1866:
 635                 freq = FREQ_1866M;
 636                 break;
 637         case 2133:
 638                 freq = FREQ_2133M;
 639                 break;
 640         default:
 641                 printf("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
 642                 return -EINVAL;
 643         }
 644
 645         ret = umc_init(umc_ch0_base, freq, 0, bd->dram_ch0_size / SZ_256M,
 646                        bd->dram_ch0_width);
 647         if (ret) {
 648                 printf("failed to initialize UMC ch0\n");
 649                 return ret;
 650         }
 651
 652         ret = umc_init(umc_ch1_base, freq, 1, bd->dram_ch1_size / SZ_256M,
 653                        bd->dram_ch1_width);
 654         if (ret) {
 655                 printf("failed to initialize UMC ch1\n");
 656                 return ret;
 657         }
 658
 659         ret = umc_init(umc_ch2_base, freq, 2, bd->dram_ch2_size / SZ_256M,
 660                        bd->dram_ch2_width);
 661         if (ret) {
 662                 printf("failed to initialize UMC ch2\n");
 663                 return ret;
 664         }
 665
 666         um_init(um_base);
 667
 668         return 0;
 669 }