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   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * UniPhier UMC (Universal Memory Controller) registers
   4  *
   5  * Copyright (C) 2011-2014 Panasonic Corporation
   6  */
   7
   8 #ifndef ARCH_UMC_REGS_H
   9 #define ARCH_UMC_REGS_H
  10
  11 #include <linux/bitops.h>
  12
  13 #define UMC_CPURST              0x00000700
  14 #define UMC_IDSRST              0x0000070C
  15 #define UMC_IXMRST              0x00000714
  16 #define UMC_HDMRST              0x00000718
  17 #define UMC_MDMRST              0x0000071C
  18 #define UMC_HDDRST              0x00000720
  19 #define UMC_MDDRST              0x00000724
  20 #define UMC_SIORST              0x00000728
  21 #define UMC_GIORST              0x0000072C
  22 #define UMC_HD2RST              0x00000734
  23 #define UMC_VIORST              0x0000073C
  24 #define UMC_FRCRST              0x00000748 /* LD4/sLD8 */
  25 #define UMC_DVCRST              0x00000748 /* Pro4 */
  26 #define UMC_RGLRST              0x00000750
  27 #define UMC_VPERST              0x00000758
  28 #define UMC_AIORST              0x00000764
  29 #define UMC_DMDRST              0x00000770
  30
  31 #define UMC_HDMCHSEL            0x00000898
  32 #define UMC_MDMCHSEL            0x0000089C
  33 #define UMC_DVCCHSEL            0x000008C8
  34 #define UMC_DMDCHSEL            0x000008F0
  35
  36 #define UMC_CLKEN_SSIF_FETCH    0x0000C060
  37 #define UMC_CLKEN_SSIF_COMQUE0  0x0000C064
  38 #define UMC_CLKEN_SSIF_COMWC0   0x0000C068
  39 #define UMC_CLKEN_SSIF_COMRC0   0x0000C06C
  40 #define UMC_CLKEN_SSIF_COMQUE1  0x0000C070
  41 #define UMC_CLKEN_SSIF_COMWC1   0x0000C074
  42 #define UMC_CLKEN_SSIF_COMRC1   0x0000C078
  43 #define UMC_CLKEN_SSIF_WC       0x0000C07C
  44 #define UMC_CLKEN_SSIF_RC       0x0000C080
  45 #define UMC_CLKEN_SSIF_DST      0x0000C084
  46
  47 #define UMC_CMDCTLA             0x00000000
  48 #define UMC_CMDCTLB             0x00000004
  49 #define UMC_INITSET             0x00000014
  50 #define   UMC_INITSET_INIT1EN           BIT(1)  /* init without power-on wait */
  51 #define   UMC_INITSET_INIT0EN           BIT(0)  /* init with power-on wait */
  52 #define UMC_INITSTAT            0x00000018
  53 #define   UMC_INITSTAT_INIT1ST          BIT(1)  /* init without power-on wait */
  54 #define   UMC_INITSTAT_INIT0ST          BIT(0)  /* init with power-on wait */
  55 #define UMC_SPCCTLA             0x00000030
  56 #define UMC_SPCCTLB             0x00000034
  57 #define UMC_SPCSETA             0x00000038
  58 #define UMC_SPCSETB             0x0000003C
  59 #define   UMC_SPCSETB_AREFMD_MASK       (0x3)   /* Auto Refresh Mode */
  60 #define   UMC_SPCSETB_AREFMD_ARB        (0x0)   /* control by arbitor */
  61 #define   UMC_SPCSETB_AREFMD_CONT       (0x1)   /* control by DRAMCONT */
  62 #define   UMC_SPCSETB_AREFMD_REG        (0x2)   /* control by register */
  63 #define UMC_SPCSETC             0x00000040
  64 #define UMC_SPCSETD             0x00000044
  65 #define UMC_SPCSTATA            0x00000050
  66 #define UMC_SPCSTATB            0x00000054
  67 #define UMC_SPCSTATC            0x00000058
  68 #define UMC_ACSSETA             0x00000060
  69 #define UMC_FLOWCTLA            0x00000400
  70 #define UMC_FLOWCTLB            0x00000404
  71 #define UMC_FLOWCTLC            0x00000408
  72 #define UMC_FLOWCTLG            0x00000508
  73 #define UMC_FLOWCTLOB0          0x00000520
  74 #define UMC_FLOWCTLOB1          0x00000524
  75 #define UMC_RDATACTL_D0         0x00000600
  76 #define   UMC_RDATACTL_RADLTY_SHIFT     4
  77 #define   UMC_RDATACTL_RADLTY_MASK      (0xf << (UMC_RDATACTL_RADLTY_SHIFT))
  78 #define   UMC_RDATACTL_RAD2LTY_SHIFT    8
  79 #define   UMC_RDATACTL_RAD2LTY_MASK     (0xf << (UMC_RDATACTL_RAD2LTY_SHIFT))
  80 #define UMC_WDATACTL_D0         0x00000604
  81 #define UMC_RDATACTL_D1         0x00000608
  82 #define UMC_WDATACTL_D1         0x0000060C
  83 #define UMC_DATASET             0x00000610
  84 #define UMC_RESPCTL             0x00000624
  85 #define UMC_DCCGCTL             0x00000720
  86 #define UMC_DICGCTLA            0x00000724
  87 #define UMC_DICGCTLB            0x00000728
  88 #define UMC_ERRMASKA            0x00000958
  89 #define UMC_ERRMASKB            0x0000095c
  90 #define UMC_BSICMAPSET          0x00000988
  91 #define UMC_DIOCTLA             0x00000C00
  92 #define   UMC_DIOCTLA_CTL_NRST          BIT(8)  /* ctl_rst_n */
  93 #define   UMC_DIOCTLA_CFG_NRST          BIT(0)  /* cfg_rst_n */
  94 #define UMC_DFICUPDCTLA         0x00000C20
  95
  96 /* UM registers */
  97 #define UMC_MBUS0               0x00080004
  98 #define UMC_MBUS1               0x00081004
  99 #define UMC_MBUS2               0x00082004
 100 #define UMC_MBUS3               0x00083004
 101
 102 /* UD registers */
 103 #define UMC_BITPERPIXELMODE_D0  0x010
 104 #define UMC_PAIR1DOFF_D0        0x054
 105
 106 #endif