2 * Copyright (C) 2012-2015 Panasonic Corporation
3 * Copyright (C) 2015-2017 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <fdt_support.h>
12 #include <linux/errno.h>
13 #include <linux/sizes.h>
18 #define pr_warn(fmt, args...) printf(fmt, ##args)
19 #define pr_err(fmt, args...) printf(fmt, ##args)
21 DECLARE_GLOBAL_DATA_PTR;
23 struct uniphier_memif_data {
25 unsigned long sparse_ch1_base;
29 static const struct uniphier_memif_data uniphier_memif_data[] = {
31 .soc_id = UNIPHIER_LD4_ID,
32 .sparse_ch1_base = 0xc0000000,
35 .soc_id = UNIPHIER_PRO4_ID,
36 .sparse_ch1_base = 0xa0000000,
39 .soc_id = UNIPHIER_SLD8_ID,
40 .sparse_ch1_base = 0xc0000000,
43 .soc_id = UNIPHIER_PRO5_ID,
44 .sparse_ch1_base = 0xc0000000,
47 .soc_id = UNIPHIER_PXS2_ID,
48 .sparse_ch1_base = 0xc0000000,
52 .soc_id = UNIPHIER_LD6B_ID,
53 .sparse_ch1_base = 0xc0000000,
57 .soc_id = UNIPHIER_LD11_ID,
58 .sparse_ch1_base = 0xc0000000,
61 .soc_id = UNIPHIER_LD20_ID,
62 .sparse_ch1_base = 0xc0000000,
66 .soc_id = UNIPHIER_PXS3_ID,
67 .sparse_ch1_base = 0xc0000000,
71 UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_memif_data, uniphier_memif_data)
73 struct uniphier_dram_map {
78 static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map)
80 const struct uniphier_memif_data *data;
84 data = uniphier_get_memif_data();
86 pr_err("unsupported SoC\n");
90 val = readl(SG_MEMCONF);
93 dram_map[0].base = CONFIG_SYS_SDRAM_BASE;
95 switch (val & SG_MEMCONF_CH0_SZ_MASK) {
96 case SG_MEMCONF_CH0_SZ_64M:
99 case SG_MEMCONF_CH0_SZ_128M:
102 case SG_MEMCONF_CH0_SZ_256M:
105 case SG_MEMCONF_CH0_SZ_512M:
108 case SG_MEMCONF_CH0_SZ_1G:
112 pr_err("error: invalid value is set to MEMCONF ch0 size\n");
116 if ((val & SG_MEMCONF_CH0_NUM_MASK) == SG_MEMCONF_CH0_NUM_2)
119 dram_map[0].size = size;
122 dram_map[1].base = dram_map[0].base + size;
124 if (val & SG_MEMCONF_SPARSEMEM) {
125 if (dram_map[1].base > data->sparse_ch1_base) {
126 pr_warn("Sparse mem is enabled, but ch0 and ch1 overlap\n");
127 pr_warn("Only ch0 is available\n");
128 dram_map[1].base = 0;
132 dram_map[1].base = data->sparse_ch1_base;
135 switch (val & SG_MEMCONF_CH1_SZ_MASK) {
136 case SG_MEMCONF_CH1_SZ_64M:
139 case SG_MEMCONF_CH1_SZ_128M:
142 case SG_MEMCONF_CH1_SZ_256M:
145 case SG_MEMCONF_CH1_SZ_512M:
148 case SG_MEMCONF_CH1_SZ_1G:
152 pr_err("error: invalid value is set to MEMCONF ch1 size\n");
156 if ((val & SG_MEMCONF_CH1_NUM_MASK) == SG_MEMCONF_CH1_NUM_2)
159 dram_map[1].size = size;
161 if (!data->have_ch2 || val & SG_MEMCONF_CH2_DISABLE)
165 dram_map[2].base = dram_map[1].base + size;
167 switch (val & SG_MEMCONF_CH2_SZ_MASK) {
168 case SG_MEMCONF_CH2_SZ_64M:
171 case SG_MEMCONF_CH2_SZ_128M:
174 case SG_MEMCONF_CH2_SZ_256M:
177 case SG_MEMCONF_CH2_SZ_512M:
180 case SG_MEMCONF_CH2_SZ_1G:
184 pr_err("error: invalid value is set to MEMCONF ch2 size\n");
188 if ((val & SG_MEMCONF_CH2_NUM_MASK) == SG_MEMCONF_CH2_NUM_2)
191 dram_map[2].size = size;
198 struct uniphier_dram_map dram_map[3] = {};
203 ret = uniphier_memconf_decode(dram_map);
207 for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
209 if (!dram_map[i].size)
213 * U-Boot relocates itself to the tail of the memory region,
214 * but it does not expect sparse memory. We use the first
215 * contiguous chunk here.
217 if (i > 0 && dram_map[i - 1].base + dram_map[i - 1].size <
221 gd->ram_size += dram_map[i].size;
227 int dram_init_banksize(void)
229 struct uniphier_dram_map dram_map[3] = {};
232 uniphier_memconf_decode(dram_map);
234 for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
235 if (i >= ARRAY_SIZE(gd->bd->bi_dram))
238 gd->bd->bi_dram[i].start = dram_map[i].base;
239 gd->bd->bi_dram[i].size = dram_map[i].size;
245 #ifdef CONFIG_OF_BOARD_SETUP
247 * The DRAM PHY requires 64 byte scratch area in each DRAM channel
248 * for its dynamic PHY training feature.
250 int ft_board_setup(void *fdt, bd_t *bd)
252 unsigned long rsv_addr;
253 const unsigned long rsv_size = 64;
256 if (uniphier_get_soc_id() != UNIPHIER_LD20_ID)
259 for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) {
260 if (!gd->bd->bi_dram[i].size)
263 rsv_addr = gd->bd->bi_dram[i].start + gd->bd->bi_dram[i].size;
264 rsv_addr -= rsv_size;
266 ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size);
270 printf(" Reserved memory region for DRAM PHY training: addr=%lx size=%lx\n",