2 * Copyright (C) 2012-2015 Panasonic Corporation
3 * Copyright (C) 2015-2017 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/errno.h>
12 #include <linux/sizes.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 struct uniphier_memif_data {
22 unsigned long sparse_ch1_base;
26 static const struct uniphier_memif_data uniphier_memif_data[] = {
28 .soc_id = UNIPHIER_SLD3_ID,
29 .sparse_ch1_base = 0xc0000000,
31 * In fact, SLD3 has DRAM ch2, but the memory regions for ch1
32 * and ch2 overlap, and host cannot get access to them at the
33 * same time. Hide the ch2 from U-Boot.
37 .soc_id = UNIPHIER_LD4_ID,
38 .sparse_ch1_base = 0xc0000000,
41 .soc_id = UNIPHIER_PRO4_ID,
42 .sparse_ch1_base = 0xa0000000,
45 .soc_id = UNIPHIER_SLD8_ID,
46 .sparse_ch1_base = 0xc0000000,
49 .soc_id = UNIPHIER_PRO5_ID,
50 .sparse_ch1_base = 0xc0000000,
53 .soc_id = UNIPHIER_PXS2_ID,
54 .sparse_ch1_base = 0xc0000000,
58 .soc_id = UNIPHIER_LD6B_ID,
59 .sparse_ch1_base = 0xc0000000,
63 .soc_id = UNIPHIER_LD11_ID,
64 .sparse_ch1_base = 0xc0000000,
67 .soc_id = UNIPHIER_LD20_ID,
68 .sparse_ch1_base = 0xc0000000,
72 .soc_id = UNIPHIER_PXS3_ID,
73 .sparse_ch1_base = 0xc0000000,
77 UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_memif_data, uniphier_memif_data)
79 static int uniphier_memconf_decode(struct uniphier_dram_ch *dram_ch)
81 const struct uniphier_memif_data *data;
85 data = uniphier_get_memif_data();
87 pr_err("unsupported SoC\n");
91 val = readl(SG_MEMCONF);
94 dram_ch[0].base = CONFIG_SYS_SDRAM_BASE;
96 switch (val & SG_MEMCONF_CH0_SZ_MASK) {
97 case SG_MEMCONF_CH0_SZ_64M:
100 case SG_MEMCONF_CH0_SZ_128M:
103 case SG_MEMCONF_CH0_SZ_256M:
106 case SG_MEMCONF_CH0_SZ_512M:
109 case SG_MEMCONF_CH0_SZ_1G:
113 pr_err("error: invalid value is set to MEMCONF ch0 size\n");
117 if ((val & SG_MEMCONF_CH0_NUM_MASK) == SG_MEMCONF_CH0_NUM_2)
120 dram_ch[0].size = size;
123 dram_ch[1].base = dram_ch[0].base + size;
125 if (val & SG_MEMCONF_SPARSEMEM) {
126 if (dram_ch[1].base > data->sparse_ch1_base) {
127 pr_warn("Sparse mem is enabled, but ch0 and ch1 overlap\n");
128 pr_warn("Only ch0 is available\n");
133 dram_ch[1].base = data->sparse_ch1_base;
136 switch (val & SG_MEMCONF_CH1_SZ_MASK) {
137 case SG_MEMCONF_CH1_SZ_64M:
140 case SG_MEMCONF_CH1_SZ_128M:
143 case SG_MEMCONF_CH1_SZ_256M:
146 case SG_MEMCONF_CH1_SZ_512M:
149 case SG_MEMCONF_CH1_SZ_1G:
153 pr_err("error: invalid value is set to MEMCONF ch1 size\n");
157 if ((val & SG_MEMCONF_CH1_NUM_MASK) == SG_MEMCONF_CH1_NUM_2)
160 dram_ch[1].size = size;
162 if (!data->have_ch2 || val & SG_MEMCONF_CH2_DISABLE)
166 dram_ch[2].base = dram_ch[1].base + size;
168 switch (val & SG_MEMCONF_CH2_SZ_MASK) {
169 case SG_MEMCONF_CH2_SZ_64M:
172 case SG_MEMCONF_CH2_SZ_128M:
175 case SG_MEMCONF_CH2_SZ_256M:
178 case SG_MEMCONF_CH2_SZ_512M:
181 case SG_MEMCONF_CH2_SZ_1G:
185 pr_err("error: invalid value is set to MEMCONF ch2 size\n");
189 if ((val & SG_MEMCONF_CH2_NUM_MASK) == SG_MEMCONF_CH2_NUM_2)
192 dram_ch[2].size = size;
199 struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH] = {};
204 ret = uniphier_memconf_decode(dram_ch);
208 for (i = 0; i < ARRAY_SIZE(dram_ch); i++) {
210 if (!dram_ch[i].size)
214 * U-Boot relocates itself to the tail of the memory region,
215 * but it does not expect sparse memory. We use the first
216 * contiguous chunk here.
219 dram_ch[i - 1].base + dram_ch[i - 1].size < dram_ch[i].base)
222 gd->ram_size += dram_ch[i].size;
228 void dram_init_banksize(void)
230 struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH] = {};
233 uniphier_memconf_decode(dram_ch);
235 for (i = 0; i < ARRAY_SIZE(dram_ch); i++) {
236 if (i >= ARRAY_SIZE(gd->bd->bi_dram))
239 gd->bd->bi_dram[i].start = dram_ch[i].base;
240 gd->bd->bi_dram[i].size = dram_ch[i].size;
244 #ifdef CONFIG_OF_BOARD_SETUP
246 * The DRAM PHY requires 64 byte scratch area in each DRAM channel
247 * for its dynamic PHY training feature.
249 int ft_board_setup(void *fdt, bd_t *bd)
251 unsigned long rsv_addr;
252 const unsigned long rsv_size = 64;
255 if (uniphier_get_soc_id() != UNIPHIER_LD20_ID)
258 for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) {
259 if (!gd->bd->bi_dram[i].size)
262 rsv_addr = gd->bd->bi_dram[i].start + gd->bd->bi_dram[i].size;
263 rsv_addr -= rsv_size;
265 ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size);
269 printf(" Reserved memory region for DRAM PHY training: addr=%lx size=%lx\n",