git.sur5r.net Git - u-boot/blob - arch/arm/mach-uniphier/early-clk/early-clk-ph1-pro5.c

   1 /*
   2  * Copyright (C) 2015 Masahiro Yamada <yamada.m@jp.panasonic.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <linux/io.h>
   8 #include <mach/init.h>
   9 #include <mach/sc-regs.h>
  10
  11 int ph1_pro5_early_clk_init(const struct uniphier_board_data *bd)
  12 {
  13         u32 tmp;
  14
  15         /*
  16          * deassert reset
  17          * UMCA2: Ch1 (DDR3)
  18          * UMCA1, UMC31: Ch0 (WIO1)
  19          * UMCA0, UMC30: Ch0 (WIO0)
  20          */
  21         tmp = readl(SC_RSTCTRL4);
  22         tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
  23                SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
  24                SC_RSTCTRL4_NRST_UMC31 | SC_RSTCTRL4_NRST_UMC30;
  25         writel(tmp, SC_RSTCTRL4);
  26         readl(SC_RSTCTRL); /* dummy read */
  27
  28         /* privide clocks */
  29         tmp = readl(SC_CLKCTRL);
  30         tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
  31         writel(tmp, SC_CLKCTRL);
  32         tmp = readl(SC_CLKCTRL4);
  33         tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC1 |
  34                SC_CLKCTRL4_CEN_UMC0;
  35         writel(tmp, SC_CLKCTRL4);
  36         readl(SC_CLKCTRL4); /* dummy read */
  37
  38         return 0;
  39 }