2 * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <linux/linkage.h>
9 #include <linux/sizes.h>
10 #include <asm/system.h>
15 mov r8, lr @ persevere link reg across call
18 * The UniPhier Boot ROM loads SPL code to the L2 cache.
19 * But CPUs can only do instruction fetch now because start.S has
20 * cleared C and M bits.
21 * First we need to turn on MMU and Dcache again to get back
24 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
25 orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
26 mcr p15, 0, r0, c1, c0, 0
28 #ifdef CONFIG_DEBUG_LL
33 * Now we are using the page table embedded in the Boot ROM.
34 * It is not handy since it is not a straight mapped table for sLD3.
35 * What we need to do next is to switch over to the page table in SPL.
37 ldr r3, =init_page_table @ page table must be 16KB aligned
39 /* Disable MMU and Dcache before switching Page Table */
40 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
41 bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache
42 mcr p15, 0, r0, c1, c0, 0
46 bl setup_init_ram @ RAM area for temporary stack pointer
48 mov lr, r8 @ restore link
49 mov pc, lr @ back to my caller
50 ENDPROC(lowlevel_init)
53 mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
55 orr r0, r0, #0x20 @ disable TTBR1
56 mcr p15, 0, r0, c2, c0, 2
58 orr r0, r3, #0x8 @ Outer Cacheability for table walks: WBWA
59 mcr p15, 0, r0, c2, c0, 0 @ TTBR0
62 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
64 mov r0, #-1 @ manager for all domains (No permission check)
65 mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
71 * TLBs was already invalidated in "../start.S"
72 * So, we don't need to invalidate it here.
74 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
75 orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable
76 mcr p15, 0, r0, c1, c0, 0
82 * For PH1-Pro4 or older SoCs, the size of WAY is 32KB.
83 * It is large enough for tmp RAM.
85 #define BOOT_RAM_SIZE (SZ_32K)
86 #define BOOT_WAY_BITS (0x00000100) /* way 8 */
90 * Touch to zero for the boot way
94 * set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order
96 ldr r0, = 0x00408006 @ touch to zero with address range
99 ldr r0, = (CONFIG_SPL_STACK - BOOT_RAM_SIZE) @ base address
102 ldr r0, = BOOT_RAM_SIZE
105 ldr r0, = BOOT_WAY_BITS
110 cmp r0, #0 @ check if the command is successfully set
111 bne 0b @ try again if an error occurs
117 bne 1b @ wait until the operation is completed
118 str r0, [r1] @ clear the complete notification flag
121 ENDPROC(setup_init_ram)