2 * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <linux/linkage.h>
9 #include <linux/sizes.h>
10 #include <asm/system.h>
12 #include <mach/arm-mpcore.h>
13 #include <mach/sbc-regs.h>
14 #include <mach/ssc-regs.h>
17 mov r8, lr @ persevere link reg across call
20 * The UniPhier Boot ROM loads SPL code to the L2 cache.
21 * But CPUs can only do instruction fetch now because start.S has
22 * cleared C and M bits.
23 * First we need to turn on MMU and Dcache again to get back
26 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
27 orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
28 mcr p15, 0, r0, c1, c0, 0
30 #ifdef CONFIG_DEBUG_LL
31 bl setup_lowlevel_debug
35 * Now we are using the page table embedded in the Boot ROM.
36 * It is not handy since it is not a straight mapped table for sLD3.
37 * What we need to do next is to switch over to the page table in SPL.
39 ldr r3, =init_page_table @ page table must be 16KB aligned
41 /* Disable MMU and Dcache before switching Page Table */
42 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
43 bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache
44 mcr p15, 0, r0, c1, c0, 0
48 #ifdef CONFIG_UNIPHIER_SMP
51 * Entry point for secondary CPUs
53 * The Boot ROM has already enabled MMU for the secondary CPUs as well
54 * as for the primary one. The MMU table embedded in the Boot ROM
55 * prohibits the DRAM access, so it is impossible to bring the
56 * secondary CPUs into DRAM directly. They must jump here into SPL,
57 * which is run on L2 cache.
60 * [primary CPU] [secondary CPUs]
61 * start from Boot ROM start from Boot ROM
62 * jump to SPL sleep in Boot ROM
63 * kick secondaries ---(sev)---> jump to SPL
64 * jump to U-Boot main sleep in SPL
66 * kick secondaries ---(sev)---> jump to Linux
69 /* branch by CPU ID */
70 mrc p15, 0, r0, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Register)
74 /* only for secondary CPUs */
75 ldr r1, =ROM_BOOT_ROMRSV2 @ The last data access to L2 cache
76 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
77 orr r0, r0, #CR_I @ Enable ICache
78 bic r0, r0, #(CR_C | CR_M) @ MMU and Dcache must be disabled
79 mcr p15, 0, r0, c1, c0, 0 @ before jumping to Linux
84 * L2 cache is shared among all the CPUs and it might be disabled by
85 * the primary one. Before that, the following 5 lines must be cached
86 * on the Icaches of the secondary CPUs.
88 0: wfe @ kicked by Linux
91 bxne r0 @ r0: Linux entry for secondary CPUs
94 ldr r1, =ROM_BOOT_ROMRSV2
95 ldr r0, =secondary_startup
97 ldr r0, [r1] @ make sure str is complete before sev
98 sev @ kick the secondary CPU
101 bl setup_init_ram @ RAM area for temporary stack pointer
103 mov lr, r8 @ restore link
104 mov pc, lr @ back to my caller
105 ENDPROC(lowlevel_init)
108 mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
110 orr r0, r0, #0x20 @ disable TTBR1
111 mcr p15, 0, r0, c2, c0, 2
113 orr r0, r3, #0x8 @ Outer Cacheability for table walks: WBWA
114 mcr p15, 0, r0, c2, c0, 0 @ TTBR0
117 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
119 mov r0, #-1 @ manager for all domains (No permission check)
120 mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
126 * TLBs was already invalidated in "../start.S"
127 * So, we don't need to invalidate it here.
129 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
130 orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable
131 mcr p15, 0, r0, c1, c0, 0
137 * For PH1-Pro4 or older SoCs, the size of WAY is 32KB.
138 * It is large enough for tmp RAM.
140 #define BOOT_RAM_SIZE (SZ_32K)
141 #define BOOT_WAY_BITS (0x00000100) /* way 8 */
143 ENTRY(setup_init_ram)
145 * Touch to zero for the boot way
149 * set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order
151 ldr r0, = 0x00408006 @ touch to zero with address range
154 ldr r0, = (CONFIG_SPL_STACK - BOOT_RAM_SIZE) @ base address
157 ldr r0, = BOOT_RAM_SIZE
160 ldr r0, = BOOT_WAY_BITS
165 cmp r0, #0 @ check if the command is successfully set
166 bne 0b @ try again if an error occurs
172 bne 1b @ wait until the operation is completed
173 str r0, [r1] @ clear the complete notification flag
176 ENDPROC(setup_init_ram)