2 * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <linux/linkage.h>
9 #include <linux/sizes.h>
10 #include <asm/system.h>
11 #include <mach/arm-mpcore.h>
12 #include <mach/sbc-regs.h>
13 #include <mach/ssc-regs.h>
16 mov r8, lr @ persevere link reg across call
19 * The UniPhier Boot ROM loads SPL code to the L2 cache.
20 * But CPUs can only do instruction fetch now because start.S has
21 * cleared C and M bits.
22 * First we need to turn on MMU and Dcache again to get back
25 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
26 orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
27 mcr p15, 0, r0, c1, c0, 0
29 #ifdef CONFIG_DEBUG_LL
34 * Now we are using the page table embedded in the Boot ROM.
35 * It is not handy since it is not a straight mapped table for sLD3.
36 * What we need to do next is to switch over to the page table in SPL.
38 ldr r3, =init_page_table @ page table must be 16KB aligned
40 /* Disable MMU and Dcache before switching Page Table */
41 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
42 bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache
43 mcr p15, 0, r0, c1, c0, 0
47 bl setup_init_ram @ RAM area for temporary stack pointer
49 mov lr, r8 @ restore link
50 mov pc, lr @ back to my caller
51 ENDPROC(lowlevel_init)
54 mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
56 orr r0, r0, #0x20 @ disable TTBR1
57 mcr p15, 0, r0, c2, c0, 2
59 orr r0, r3, #0x8 @ Outer Cacheability for table walks: WBWA
60 mcr p15, 0, r0, c2, c0, 0 @ TTBR0
63 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
65 mov r0, #-1 @ manager for all domains (No permission check)
66 mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
72 * TLBs was already invalidated in "../start.S"
73 * So, we don't need to invalidate it here.
75 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
76 orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable
77 mcr p15, 0, r0, c1, c0, 0
83 * For PH1-Pro4 or older SoCs, the size of WAY is 32KB.
84 * It is large enough for tmp RAM.
86 #define BOOT_RAM_SIZE (SZ_32K)
87 #define BOOT_WAY_BITS (0x00000100) /* way 8 */
91 * Touch to zero for the boot way
95 * set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order
97 ldr r0, = 0x00408006 @ touch to zero with address range
100 ldr r0, = (CONFIG_SPL_STACK - BOOT_RAM_SIZE) @ base address
103 ldr r0, = BOOT_RAM_SIZE
106 ldr r0, = BOOT_WAY_BITS
111 cmp r0, #0 @ check if the command is successfully set
112 bne 0b @ try again if an error occurs
118 bne 1b @ wait until the operation is completed
119 str r0, [r1] @ clear the complete notification flag
122 ENDPROC(setup_init_ram)