git.sur5r.net Git - u-boot/blob - arch/arm/mach-uniphier/ph1-pro4/pll_init.c

   1 /*
   2  * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <linux/io.h>
   9 #include <mach/sc-regs.h>
  10 #include <mach/sg-regs.h>
  11
  12 #undef DPLL_SSC_RATE_1PER
  13
  14 static void dpll_init(void)
  15 {
  16         u32 tmp;
  17
  18         /*
  19          * Set Frequency
  20          * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
  21          * to FOUT ( DPLLCTRL.bit[29:20] )
  22          */
  23         tmp = readl(SC_DPLLCTRL);
  24         tmp &= ~(0x000f0000);
  25 #if CONFIG_DDR_FREQ == 1600
  26         tmp |= 0x000c0000;
  27 #elif CONFIG_DDR_FREQ == 1333
  28         tmp |= 0x000d0000;
  29 #else
  30 # error "Unsupported frequency"
  31 #endif
  32
  33         /*
  34          * Set Moduration rate
  35          * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
  36          */
  37 #if defined(DPLL_SSC_RATE_1PER)
  38         tmp &= ~0x00008000;
  39 #else
  40         tmp |= 0x00008000;
  41 #endif
  42         writel(tmp, SC_DPLLCTRL);
  43
  44         tmp = readl(SC_DPLLCTRL2);
  45         tmp |= SC_DPLLCTRL2_NRSTDS;
  46         writel(tmp, SC_DPLLCTRL2);
  47 }
  48
  49 static void vpll_init(void)
  50 {
  51         u32 tmp, clk_mode_axosel;
  52
  53         /* Set VPLL27A &  VPLL27B */
  54         tmp = readl(SG_PINMON0);
  55         clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
  56
  57         /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
  58         if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
  59             clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
  60                 return;
  61
  62         /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
  63         tmp = readl(SC_VPLL27ACTRL);
  64         tmp |= 0x00000001;
  65         writel(tmp, SC_VPLL27ACTRL);
  66         tmp = readl(SC_VPLL27BCTRL);
  67         tmp |= 0x00000001;
  68         writel(tmp, SC_VPLL27BCTRL);
  69
  70         /* Unset VPLA_K_LD and VPLB_K_LD bit */
  71         tmp = readl(SC_VPLL27ACTRL3);
  72         tmp &= ~0x10000000;
  73         writel(tmp, SC_VPLL27ACTRL3);
  74         tmp = readl(SC_VPLL27BCTRL3);
  75         tmp &= ~0x10000000;
  76         writel(tmp, SC_VPLL27BCTRL3);
  77
  78         /* Set VPLA_M and VPLB_M to 0x20 */
  79         tmp = readl(SC_VPLL27ACTRL2);
  80         tmp &= ~0x0000007f;
  81         tmp |= 0x00000020;
  82         writel(tmp, SC_VPLL27ACTRL2);
  83         tmp = readl(SC_VPLL27BCTRL2);
  84         tmp &= ~0x0000007f;
  85         tmp |= 0x00000020;
  86         writel(tmp, SC_VPLL27BCTRL2);
  87
  88         if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
  89             clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
  90                 /* Set VPLA_K and VPLB_K for AXO: 25MHz */
  91                 tmp = readl(SC_VPLL27ACTRL3);
  92                 tmp &= ~0x000fffff;
  93                 tmp |= 0x00066666;
  94                 writel(tmp, SC_VPLL27ACTRL3);
  95                 tmp = readl(SC_VPLL27BCTRL3);
  96                 tmp &= ~0x000fffff;
  97                 tmp |= 0x00066666;
  98                 writel(tmp, SC_VPLL27BCTRL3);
  99         } else {
 100                 /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
 101                 tmp = readl(SC_VPLL27ACTRL3);
 102                 tmp &= ~0x000fffff;
 103                 tmp |= 0x000f5800;
 104                 writel(tmp, SC_VPLL27ACTRL3);
 105                 tmp = readl(SC_VPLL27BCTRL3);
 106                 tmp &= ~0x000fffff;
 107                 tmp |= 0x000f5800;
 108                 writel(tmp, SC_VPLL27BCTRL3);
 109         }
 110
 111         /* wait 1 usec */
 112         udelay(1);
 113
 114         /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
 115         tmp = readl(SC_VPLL27ACTRL3);
 116         tmp |= 0x10000000;
 117         writel(tmp, SC_VPLL27ACTRL3);
 118         tmp = readl(SC_VPLL27BCTRL3);
 119         tmp |= 0x10000000;
 120         writel(tmp, SC_VPLL27BCTRL3);
 121
 122         /* Unset VPLA_SNRST and VPLB_SNRST bit */
 123         tmp = readl(SC_VPLL27ACTRL2);
 124         tmp |= 0x10000000;
 125         writel(tmp, SC_VPLL27ACTRL2);
 126         tmp = readl(SC_VPLL27BCTRL2);
 127         tmp |= 0x10000000;
 128         writel(tmp, SC_VPLL27BCTRL2);
 129
 130         /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
 131         tmp = readl(SC_VPLL27ACTRL);
 132         tmp &= ~0x00000001;
 133         writel(tmp, SC_VPLL27ACTRL);
 134         tmp = readl(SC_VPLL27BCTRL);
 135         tmp &= ~0x00000001;
 136         writel(tmp, SC_VPLL27BCTRL);
 137 }
 138
 139 void pll_init(void)
 140 {
 141         dpll_init();
 142         vpll_init();
 143
 144         /*
 145          * Wait 500 usec until dpll get stable
 146          * We wait 1 usec in vpll_init() so 1 usec can be saved here.
 147          */
 148         udelay(499);
 149 }