2 * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <mach/bcu-regs.h>
11 #define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
17 writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
18 writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
19 writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
21 * 0xe0000000-0xefffffff: Ex-bus
22 * 0xf0000000-0xfbffffff: ASM bus
23 * 0xfc000000-0xffffffff: OCM bus
25 writel(0x24440000, BCSCR5);
27 /* Specify DDR channel */
28 shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4;
29 writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
32 writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
35 writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */