2 * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <mach/init.h>
11 #include <mach/sc-regs.h>
12 #include <mach/sg-regs.h>
14 #undef DPLL_SSC_RATE_1PER
16 static int dpll_init(unsigned int dram_freq)
22 * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
23 * to FOUT (DPLLCTRL.bit[29:20])
25 tmp = readl(SC_DPLLCTRL);
35 pr_err("Unsupported frequency");
39 #if defined(DPLL_SSC_RATE_1PER)
40 tmp &= ~SC_DPLLCTRL_SSC_RATE;
42 tmp |= SC_DPLLCTRL_SSC_RATE;
44 writel(tmp, SC_DPLLCTRL);
46 tmp = readl(SC_DPLLCTRL2);
47 tmp |= SC_DPLLCTRL2_NRSTDS;
48 writel(tmp, SC_DPLLCTRL2);
53 static void upll_init(void)
55 u32 tmp, clk_mode_upll, clk_mode_axosel;
57 tmp = readl(SG_PINMON0);
58 clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
59 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
61 /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
62 tmp = readl(SC_UPLLCTRL);
64 writel(tmp, SC_UPLLCTRL);
66 if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
67 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
68 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
73 /* AXO: default 24.576MHz */
79 writel(tmp, SC_UPLLCTRL);
81 /* set 1 to K_LD(UPLLCTRL.bit[27]) */
83 writel(tmp, SC_UPLLCTRL);
88 /* set 1 to SNRT(UPLLCTRL.bit[28]) */
90 writel(tmp, SC_UPLLCTRL);
93 static void vpll_init(void)
95 u32 tmp, clk_mode_axosel;
97 tmp = readl(SG_PINMON0);
98 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
100 /* set 1 to VPLA27WP and VPLA27WP */
101 tmp = readl(SC_VPLL27ACTRL);
103 writel(tmp, SC_VPLL27ACTRL);
104 tmp = readl(SC_VPLL27BCTRL);
106 writel(tmp, SC_VPLL27BCTRL);
108 /* Set 0 to VPLA_K_LD and VPLB_K_LD */
109 tmp = readl(SC_VPLL27ACTRL3);
111 writel(tmp, SC_VPLL27ACTRL3);
112 tmp = readl(SC_VPLL27BCTRL3);
114 writel(tmp, SC_VPLL27BCTRL3);
116 /* Set 0 to VPLA_SNRST and VPLB_SNRST */
117 tmp = readl(SC_VPLL27ACTRL2);
119 writel(tmp, SC_VPLL27ACTRL2);
120 tmp = readl(SC_VPLL27BCTRL2);
122 writel(tmp, SC_VPLL27BCTRL2);
124 /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
125 tmp = readl(SC_VPLL27ACTRL2);
128 writel(tmp, SC_VPLL27ACTRL2);
129 tmp = readl(SC_VPLL27BCTRL2);
132 writel(tmp, SC_VPLL27BCTRL2);
134 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
135 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
137 tmp = readl(SC_VPLL27ACTRL3);
140 writel(tmp, SC_VPLL27ACTRL3);
141 tmp = readl(SC_VPLL27BCTRL3);
144 writel(tmp, SC_VPLL27BCTRL3);
146 /* AXO: default 24.576MHz */
147 tmp = readl(SC_VPLL27ACTRL3);
150 writel(tmp, SC_VPLL27ACTRL3);
151 tmp = readl(SC_VPLL27BCTRL3);
154 writel(tmp, SC_VPLL27BCTRL3);
157 /* Set 1 to VPLA_K_LD and VPLB_K_LD */
158 tmp = readl(SC_VPLL27ACTRL3);
160 writel(tmp, SC_VPLL27ACTRL3);
161 tmp = readl(SC_VPLL27BCTRL3);
163 writel(tmp, SC_VPLL27BCTRL3);
168 /* Set 0 to VPLA_SNRST and VPLB_SNRST */
169 tmp = readl(SC_VPLL27ACTRL2);
171 writel(tmp, SC_VPLL27ACTRL2);
172 tmp = readl(SC_VPLL27BCTRL2);
174 writel(tmp, SC_VPLL27BCTRL2);
176 /* set 0 to VPLA27WP and VPLA27WP */
177 tmp = readl(SC_VPLL27ACTRL);
179 writel(tmp, SC_VPLL27ACTRL);
180 tmp = readl(SC_VPLL27BCTRL);
182 writel(tmp, SC_VPLL27BCTRL);
185 int ph1_ld4_pll_init(const struct uniphier_board_data *bd)
189 ret = dpll_init(bd->dram_freq);
196 * Wait 500 usec until dpll get stable
197 * We wait 10 usec in upll_init() and vpll_init()
198 * so 20 usec can be saved here.