2 * UniPhier SC (System Control) block registers for ARMv8 SoCs
4 * Copyright (C) 2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: GPL-2.0+
13 #define SC_BASE_ADDR 0x61840000
16 #define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* LD11/20: CPU/ARM */
17 #define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* LD11/20: misc */
18 #define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* LD20: IPP */
19 #define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* LD11/20: Video codec */
20 #define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD11 */
21 #define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD20: VPE etc. */
22 #define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* LD20: GPU/Mali */
23 #define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* LD11: DDR memory */
24 #define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* LD20: DDR memory 0 */
25 #define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* LD20: DDR memory 1 */
26 #define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* LD20: DDR memory 2 */
28 /* PLL type: VPLL27 */
29 #define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
30 #define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
33 #define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540)
34 #define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0)
36 #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
37 #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
38 #define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
39 #define SC_RSTCTRL4_ETHER (1 << 6)
40 #define SC_RSTCTRL4_NAND (1 << 0)
41 #define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010)
42 #define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014)
43 #define SC_RSTCTRL7 (SC_BASE_ADDR | 0x2018)
44 #define SC_RSTCTRL7_UMCSB (1 << 16)
45 #define SC_RSTCTRL7_UMCA2 (1 << 10)
46 #define SC_RSTCTRL7_UMCA1 (1 << 9)
47 #define SC_RSTCTRL7_UMCA0 (1 << 8)
48 #define SC_RSTCTRL7_UMC32 (1 << 2)
49 #define SC_RSTCTRL7_UMC31 (1 << 1)
50 #define SC_RSTCTRL7_UMC30 (1 << 0)
52 #define SC_CLKCTRL (SC_BASE_ADDR | 0x2100)
53 #define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108)
54 #define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
55 #define SC_CLKCTRL4_PERI (1 << 7)
56 #define SC_CLKCTRL4_ETHER (1 << 6)
57 #define SC_CLKCTRL4_NAND (1 << 0)
58 #define SC_CLKCTRL5 (SC_BASE_ADDR | 0x2110)
59 #define SC_CLKCTRL6 (SC_BASE_ADDR | 0x2114)
60 #define SC_CLKCTRL7 (SC_BASE_ADDR | 0x2118)
61 #define SC_CLKCTRL7_UMCSB (1 << 16)
62 #define SC_CLKCTRL7_UMC32 (1 << 2)
63 #define SC_CLKCTRL7_UMC31 (1 << 1)
64 #define SC_CLKCTRL7_UMC30 (1 << 0)
66 #define SC_CA72_GEARST (SC_BASE_ADDR | 0x8080)
67 #define SC_CA72_GEARSET (SC_BASE_ADDR | 0x8084)
68 #define SC_CA72_GEARUPD (SC_BASE_ADDR | 0x8088)
69 #define SC_CA53_GEARST (SC_BASE_ADDR | 0x8080)
70 #define SC_CA53_GEARSET (SC_BASE_ADDR | 0x8084)
71 #define SC_CA53_GEARUPD (SC_BASE_ADDR | 0x8088)
72 #define SC_CA_GEARUPD (1 << 0)
74 #endif /* SC64_REGS_H */