2 * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/sizes.h>
11 #include <mach/init.h>
12 #include <mach/umc-regs.h>
13 #include <mach/ddrphy-regs.h>
15 static void umc_start_ssif(void __iomem *ssif_base)
17 writel(0x00000000, ssif_base + 0x0000b004);
18 writel(0xffffffff, ssif_base + 0x0000c004);
19 writel(0x000fffcf, ssif_base + 0x0000c008);
20 writel(0x00000001, ssif_base + 0x0000b000);
21 writel(0x00000001, ssif_base + 0x0000c000);
22 writel(0x03010101, ssif_base + UMC_MDMCHSEL);
23 writel(0x03010100, ssif_base + UMC_DMDCHSEL);
25 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
26 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
27 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
28 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
29 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
30 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
31 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
32 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
33 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
34 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
36 writel(0x00000001, ssif_base + UMC_CPURST);
37 writel(0x00000001, ssif_base + UMC_IDSRST);
38 writel(0x00000001, ssif_base + UMC_IXMRST);
39 writel(0x00000001, ssif_base + UMC_MDMRST);
40 writel(0x00000001, ssif_base + UMC_MDDRST);
41 writel(0x00000001, ssif_base + UMC_SIORST);
42 writel(0x00000001, ssif_base + UMC_VIORST);
43 writel(0x00000001, ssif_base + UMC_FRCRST);
44 writel(0x00000001, ssif_base + UMC_RGLRST);
45 writel(0x00000001, ssif_base + UMC_AIORST);
46 writel(0x00000001, ssif_base + UMC_DMDRST);
49 static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
53 writel(0x45990b11, dramcont + UMC_CMDCTLA);
54 writel(0x16958924, dramcont + UMC_CMDCTLB);
55 writel(0x5101046A, dramcont + UMC_INITCTLA);
58 writel(0x27028B0A, dramcont + UMC_INITCTLB);
60 writel(0x38028B0A, dramcont + UMC_INITCTLB);
62 writel(0x000FF0FF, dramcont + UMC_INITCTLC);
63 writel(0x00000b51, dramcont + UMC_DRMMR0);
64 } else if (freq == 1600) {
65 writel(0x36BB0F17, dramcont + UMC_CMDCTLA);
66 writel(0x18C6AA24, dramcont + UMC_CMDCTLB);
67 writel(0x5101387F, dramcont + UMC_INITCTLA);
70 writel(0x2F030D3F, dramcont + UMC_INITCTLB);
72 writel(0x43030D3F, dramcont + UMC_INITCTLB);
74 writel(0x00FF00FF, dramcont + UMC_INITCTLC);
75 writel(0x00000d71, dramcont + UMC_DRMMR0);
78 writel(0x00000006, dramcont + UMC_DRMMR1);
81 writel(0x00000290, dramcont + UMC_DRMMR2);
82 else if (freq == 1600)
83 writel(0x00000298, dramcont + UMC_DRMMR2);
85 writel(0x00000800, dramcont + UMC_DRMMR3);
89 writel(0x00240512, dramcont + UMC_SPCCTLA);
91 writel(0x00350512, dramcont + UMC_SPCCTLA);
93 writel(0x00ff0006, dramcont + UMC_SPCCTLB);
94 writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
95 } else if (freq == 1600) {
97 writel(0x002B0617, dramcont + UMC_SPCCTLA);
99 writel(0x003F0617, dramcont + UMC_SPCCTLA);
101 writel(0x00ff0008, dramcont + UMC_SPCCTLB);
102 writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
105 writel(0x04060806, dramcont + UMC_WDATACTL_D0);
106 writel(0x04a02000, dramcont + UMC_DATASET);
107 writel(0x00000000, ca_base + 0x2300);
108 writel(0x00400020, dramcont + UMC_DCCGCTL);
109 writel(0x00000003, dramcont + 0x7000);
110 writel(0x0000000f, dramcont + 0x8000);
111 writel(0x000000c3, dramcont + 0x8004);
112 writel(0x00000071, dramcont + 0x8008);
113 writel(0x0000003b, dramcont + UMC_DICGCTLA);
114 writel(0x020a0808, dramcont + UMC_DICGCTLB);
115 writel(0x00000004, dramcont + UMC_FLOWCTLG);
116 writel(0x80000201, ca_base + 0xc20);
117 writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
118 writel(0x00200000, dramcont + UMC_FLOWCTLB);
119 writel(0x00004444, dramcont + UMC_FLOWCTLC);
120 writel(0x200a0a00, dramcont + UMC_SPCSETB);
121 writel(0x00000000, dramcont + UMC_SPCSETD);
122 writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
125 static int umc_init_sub(int freq, int size_ch0, int size_ch1)
127 void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
128 void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
129 void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
130 void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
131 void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
132 void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
133 void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
135 umc_dram_init_start(dramcont0);
136 umc_dram_init_start(dramcont1);
137 umc_dram_init_poll(dramcont0);
138 umc_dram_init_poll(dramcont1);
140 writel(0x00000101, dramcont0 + UMC_DIOCTLA);
142 ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0);
144 ddrphy_prepare_training(phy0_0, 0);
145 ddrphy_training(phy0_0);
147 writel(0x00000101, dramcont1 + UMC_DIOCTLA);
149 ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1);
151 ddrphy_prepare_training(phy1_0, 1);
152 ddrphy_training(phy1_0);
154 umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
155 umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
157 umc_start_ssif(ssif_base);
162 int ph1_ld4_umc_init(const struct uniphier_board_data *bd)
164 if ((bd->dram_ch0_size == SZ_128M || bd->dram_ch0_size == SZ_256M) &&
165 (bd->dram_ch1_size == SZ_128M || bd->dram_ch1_size == SZ_256M) &&
166 (bd->dram_freq == 1333 || bd->dram_freq == 1600) &&
167 bd->dram_ch0_width == 16 && bd->dram_ch1_width == 16) {
168 return umc_init_sub(bd->dram_freq,
169 bd->dram_ch0_size / SZ_128M,
170 bd->dram_ch1_size / SZ_128M);
172 pr_err("Unsupported DDR configuration\n");