git.sur5r.net Git - u-boot/blob - arch/arm/mach-zynq/clk.c

   1 /*
   2  * Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com>
   3  * Copyright (C) 2013 Xilinx, Inc. All rights reserved.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/hardware.h>
  11 #include <asm/arch/clk.h>
  12
  13 /* Board oscillator frequency */
  14 #ifndef CONFIG_ZYNQ_PS_CLK_FREQ
  15 # define CONFIG_ZYNQ_PS_CLK_FREQ        33333333UL
  16 #endif
  17
  18 /* Register bitfield defines */
  19 #define PLLCTRL_FBDIV_MASK      0x7f000
  20 #define PLLCTRL_FBDIV_SHIFT     12
  21 #define PLLCTRL_BPFORCE_MASK    (1 << 4)
  22 #define PLLCTRL_PWRDWN_MASK     2
  23 #define PLLCTRL_PWRDWN_SHIFT    1
  24 #define PLLCTRL_RESET_MASK      1
  25 #define PLLCTRL_RESET_SHIFT     0
  26
  27 #define ZYNQ_CLK_MAXDIV         0x3f
  28 #define CLK_CTRL_DIV1_SHIFT     20
  29 #define CLK_CTRL_DIV1_MASK      (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
  30 #define CLK_CTRL_DIV0_SHIFT     8
  31 #define CLK_CTRL_DIV0_MASK      (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
  32 #define CLK_CTRL_SRCSEL_SHIFT   4
  33 #define CLK_CTRL_SRCSEL_MASK    (0x3 << CLK_CTRL_SRCSEL_SHIFT)
  34
  35 #define CLK_CTRL_DIV2X_SHIFT    26
  36 #define CLK_CTRL_DIV2X_MASK     (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV2X_SHIFT)
  37 #define CLK_CTRL_DIV3X_SHIFT    20
  38 #define CLK_CTRL_DIV3X_MASK     (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV3X_SHIFT)
  39
  40 #define ZYNQ_CLKMUX_SEL_0       0
  41 #define ZYNQ_CLKMUX_SEL_1       1
  42 #define ZYNQ_CLKMUX_SEL_2       2
  43 #define ZYNQ_CLKMUX_SEL_3       3
  44
  45 DECLARE_GLOBAL_DATA_PTR;
  46
  47 struct clk;
  48
  49 /**
  50  * struct zynq_clk_ops:
  51  * @set_rate:   Function pointer to set_rate() implementation
  52  * @get_rate:   Function pointer to get_rate() implementation
  53  */
  54 struct zynq_clk_ops {
  55         int (*set_rate)(struct clk *clk, unsigned long rate);
  56         unsigned long (*get_rate)(struct clk *clk);
  57 };
  58
  59 /**
  60  * struct clk:
  61  * @frequency:  Currenct frequency
  62  * @parent:     Parent clock
  63  * @flags:      Clock flags
  64  * @reg:        Clock control register
  65  * @ops:        Clock operations
  66  */
  67 struct clk {
  68         unsigned long   frequency;
  69         enum zynq_clk   parent;
  70         unsigned int    flags;
  71         u32             *reg;
  72         struct zynq_clk_ops     ops;
  73 };
  74 #define ZYNQ_CLK_FLAGS_HAS_2_DIVS       1
  75
  76 static struct clk clks[clk_max];
  77
  78 static const char * const clk_names[clk_max] = {
  79         "armpll", "ddrpll", "iopll",
  80         "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x",
  81         "ddr2x", "ddr3x", "dci",
  82         "lqspi", "smc", "pcap", "gem0", "gem1",
  83         "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
  84         "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma",
  85         "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper",
  86         "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper",
  87         "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper",
  88         "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper",
  89         "smc_aper", "swdt", "dbg_trc", "dbg_apb"
  90 };
  91
  92 /**
  93  * __zynq_clk_cpu_get_parent() - Decode clock multiplexer
  94  * @srcsel:     Mux select value
  95  * Returns the clock identifier associated with the selected mux input.
  96  */
  97 static int __zynq_clk_cpu_get_parent(unsigned int srcsel)
  98 {
  99         unsigned int ret;
 100
 101         switch (srcsel) {
 102         case ZYNQ_CLKMUX_SEL_0:
 103         case ZYNQ_CLKMUX_SEL_1:
 104                 ret = armpll_clk;
 105                 break;
 106         case ZYNQ_CLKMUX_SEL_2:
 107                 ret = ddrpll_clk;
 108                 break;
 109         case ZYNQ_CLKMUX_SEL_3:
 110                 ret = iopll_clk;
 111                 break;
 112         default:
 113                 ret = armpll_clk;
 114                 break;
 115         }
 116
 117         return ret;
 118 }
 119
 120 /**
 121  * ddr2x_get_rate() - Get clock rate of DDR2x clock
 122  * @clk:        Clock handle
 123  * Returns the current clock rate of @clk.
 124  */
 125 static unsigned long ddr2x_get_rate(struct clk *clk)
 126 {
 127         u32 clk_ctrl = readl(clk->reg);
 128         u32 div = (clk_ctrl & CLK_CTRL_DIV2X_MASK) >> CLK_CTRL_DIV2X_SHIFT;
 129
 130         return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div);
 131 }
 132
 133 /**
 134  * ddr3x_get_rate() - Get clock rate of DDR3x clock
 135  * @clk:        Clock handle
 136  * Returns the current clock rate of @clk.
 137  */
 138 static unsigned long ddr3x_get_rate(struct clk *clk)
 139 {
 140         u32 clk_ctrl = readl(clk->reg);
 141         u32 div = (clk_ctrl & CLK_CTRL_DIV3X_MASK) >> CLK_CTRL_DIV3X_SHIFT;
 142
 143         return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div);
 144 }
 145
 146 static void init_ddr_clocks(void)
 147 {
 148         u32 div0, div1;
 149         unsigned long prate = zynq_clk_get_rate(ddrpll_clk);
 150         u32 clk_ctrl = readl(&slcr_base->ddr_clk_ctrl);
 151
 152         /* DDR2x */
 153         clks[ddr2x_clk].reg = &slcr_base->ddr_clk_ctrl;
 154         clks[ddr2x_clk].parent = ddrpll_clk;
 155         clks[ddr2x_clk].frequency = ddr2x_get_rate(&clks[ddr2x_clk]);
 156         clks[ddr2x_clk].ops.get_rate = ddr2x_get_rate;
 157
 158         /* DDR3x */
 159         clks[ddr3x_clk].reg = &slcr_base->ddr_clk_ctrl;
 160         clks[ddr3x_clk].parent = ddrpll_clk;
 161         clks[ddr3x_clk].frequency = ddr3x_get_rate(&clks[ddr3x_clk]);
 162         clks[ddr3x_clk].ops.get_rate = ddr3x_get_rate;
 163
 164         /* DCI */
 165         clk_ctrl = readl(&slcr_base->dci_clk_ctrl);
 166         div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 167         div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
 168         clks[dci_clk].reg = &slcr_base->dci_clk_ctrl;
 169         clks[dci_clk].parent = ddrpll_clk;
 170         clks[dci_clk].frequency = DIV_ROUND_CLOSEST(
 171                         DIV_ROUND_CLOSEST(prate, div0), div1);
 172
 173         gd->bd->bi_ddr_freq = clks[ddr3x_clk].frequency / 1000000;
 174 }
 175
 176 static void init_cpu_clocks(void)
 177 {
 178         int clk_621;
 179         u32 reg, div, srcsel;
 180         enum zynq_clk parent;
 181
 182         reg = readl(&slcr_base->arm_clk_ctrl);
 183         clk_621 = readl(&slcr_base->clk_621_true) & 1;
 184         div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 185         srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
 186         parent = __zynq_clk_cpu_get_parent(srcsel);
 187
 188         /* cpu clocks */
 189         clks[cpu_6or4x_clk].reg = &slcr_base->arm_clk_ctrl;
 190         clks[cpu_6or4x_clk].parent = parent;
 191         clks[cpu_6or4x_clk].frequency = DIV_ROUND_CLOSEST(
 192                         zynq_clk_get_rate(parent), div);
 193
 194         clks[cpu_3or2x_clk].reg = &slcr_base->arm_clk_ctrl;
 195         clks[cpu_3or2x_clk].parent = cpu_6or4x_clk;
 196         clks[cpu_3or2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) / 2;
 197
 198         clks[cpu_2x_clk].reg = &slcr_base->arm_clk_ctrl;
 199         clks[cpu_2x_clk].parent = cpu_6or4x_clk;
 200         clks[cpu_2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) /
 201                         (2 + clk_621);
 202
 203         clks[cpu_1x_clk].reg = &slcr_base->arm_clk_ctrl;
 204         clks[cpu_1x_clk].parent = cpu_6or4x_clk;
 205         clks[cpu_1x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) /
 206                         (4 + 2 * clk_621);
 207 }
 208
 209 /**
 210  * periph_calc_two_divs() - Calculate clock dividers
 211  * @cur_rate:   Current clock rate
 212  * @tgt_rate:   Target clock rate
 213  * @prate:      Parent clock rate
 214  * @div0:       First divider (output)
 215  * @div1:       Second divider (output)
 216  * Returns the actual clock rate possible.
 217  *
 218  * Calculates clock dividers for clocks with two 6-bit dividers.
 219  */
 220 static unsigned long periph_calc_two_divs(unsigned long cur_rate,
 221                 unsigned long tgt_rate, unsigned long prate, u32 *div0,
 222                 u32 *div1)
 223 {
 224         long err, best_err = (long)(~0UL >> 1);
 225         unsigned long rate, best_rate = 0;
 226         u32 d0, d1;
 227
 228         for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) {
 229                 for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) {
 230                         rate = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(prate, d0),
 231                                         d1);
 232                         err = abs(rate - tgt_rate);
 233
 234                         if (err < best_err) {
 235                                 *div0 = d0;
 236                                 *div1 = d1;
 237                                 best_err = err;
 238                                 best_rate = rate;
 239                         }
 240                 }
 241         }
 242
 243         return best_rate;
 244 }
 245
 246 /**
 247  * zynq_clk_periph_set_rate() - Set clock rate
 248  * @clk:        Handle of the peripheral clock
 249  * @rate:       New clock rate
 250  * Sets the clock frequency of @clk to @rate. Returns zero on success.
 251  */
 252 static int zynq_clk_periph_set_rate(struct clk *clk,
 253                 unsigned long rate)
 254 {
 255         u32 ctrl, div0 = 0, div1 = 0;
 256         unsigned long prate, new_rate, cur_rate = clk->frequency;
 257
 258         ctrl = readl(clk->reg);
 259         prate = zynq_clk_get_rate(clk->parent);
 260         ctrl &= ~CLK_CTRL_DIV0_MASK;
 261
 262         if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS) {
 263                 ctrl &= ~CLK_CTRL_DIV1_MASK;
 264                 new_rate = periph_calc_two_divs(cur_rate, rate, prate, &div0,
 265                                 &div1);
 266                 ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;
 267         } else {
 268                 div0 = DIV_ROUND_CLOSEST(prate, rate);
 269                 div0 &= ZYNQ_CLK_MAXDIV;
 270                 new_rate = DIV_ROUND_CLOSEST(rate, div0);
 271         }
 272
 273         /* write new divs to hardware */
 274         ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;
 275         writel(ctrl, clk->reg);
 276
 277         /* update frequency in clk framework */
 278         clk->frequency = new_rate;
 279
 280         return 0;
 281 }
 282
 283 /**
 284  * zynq_clk_periph_get_rate() - Get clock rate
 285  * @clk:        Handle of the peripheral clock
 286  * Returns the current clock rate of @clk.
 287  */
 288 static unsigned long zynq_clk_periph_get_rate(struct clk *clk)
 289 {
 290         u32 clk_ctrl = readl(clk->reg);
 291         u32 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 292         u32 div1 = 1;
 293
 294         if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS)
 295                 div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
 296
 297         /* a register value of zero == division by 1 */
 298         if (!div0)
 299                 div0 = 1;
 300         if (!div1)
 301                 div1 = 1;
 302
 303         return
 304                 DIV_ROUND_CLOSEST(
 305                         DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div0),
 306                         div1);
 307 }
 308
 309 /**
 310  * __zynq_clk_periph_get_parent() - Decode clock multiplexer
 311  * @srcsel:     Mux select value
 312  * Returns the clock identifier associated with the selected mux input.
 313  */
 314 static enum zynq_clk __zynq_clk_periph_get_parent(u32 srcsel)
 315 {
 316         switch (srcsel) {
 317         case ZYNQ_CLKMUX_SEL_0:
 318         case ZYNQ_CLKMUX_SEL_1:
 319                 return iopll_clk;
 320         case ZYNQ_CLKMUX_SEL_2:
 321                 return armpll_clk;
 322         case ZYNQ_CLKMUX_SEL_3:
 323                 return ddrpll_clk;
 324         default:
 325                 return 0;
 326         }
 327 }
 328
 329 /**
 330  * zynq_clk_periph_get_parent() - Decode clock multiplexer
 331  * @clk:        Clock handle
 332  * Returns the clock identifier associated with the selected mux input.
 333  */
 334 static enum zynq_clk zynq_clk_periph_get_parent(struct clk *clk)
 335 {
 336         u32 clk_ctrl = readl(clk->reg);
 337         u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
 338
 339         return __zynq_clk_periph_get_parent(srcsel);
 340 }
 341
 342 /**
 343  * zynq_clk_register_periph_clk() - Set up a peripheral clock with the framework
 344  * @clk:        Pointer to struct clk for the clock
 345  * @ctrl:       Clock control register
 346  * @two_divs:   Indicates whether the clock features one or two dividers
 347  */
 348 static int zynq_clk_register_periph_clk(struct clk *clk, u32 *ctrl,
 349                 bool two_divs)
 350 {
 351         clk->reg = ctrl;
 352         if (two_divs)
 353                 clk->flags = ZYNQ_CLK_FLAGS_HAS_2_DIVS;
 354         clk->parent = zynq_clk_periph_get_parent(clk);
 355         clk->frequency = zynq_clk_periph_get_rate(clk);
 356         clk->ops.get_rate = zynq_clk_periph_get_rate;
 357         clk->ops.set_rate = zynq_clk_periph_set_rate;
 358
 359         return 0;
 360 }
 361
 362 static void init_periph_clocks(void)
 363 {
 364         zynq_clk_register_periph_clk(&clks[gem0_clk],
 365                                      &slcr_base->gem0_clk_ctrl, 1);
 366         zynq_clk_register_periph_clk(&clks[gem1_clk],
 367                                      &slcr_base->gem1_clk_ctrl, 1);
 368
 369         zynq_clk_register_periph_clk(&clks[smc_clk],
 370                                      &slcr_base->smc_clk_ctrl, 0);
 371
 372         zynq_clk_register_periph_clk(&clks[lqspi_clk],
 373                                      &slcr_base->lqspi_clk_ctrl, 0);
 374
 375         zynq_clk_register_periph_clk(&clks[sdio0_clk],
 376                                      &slcr_base->sdio_clk_ctrl, 0);
 377         zynq_clk_register_periph_clk(&clks[sdio1_clk],
 378                                      &slcr_base->sdio_clk_ctrl, 0);
 379
 380         zynq_clk_register_periph_clk(&clks[spi0_clk],
 381                                      &slcr_base->spi_clk_ctrl, 0);
 382         zynq_clk_register_periph_clk(&clks[spi1_clk],
 383                                      &slcr_base->spi_clk_ctrl, 0);
 384
 385         zynq_clk_register_periph_clk(&clks[uart0_clk],
 386                                      &slcr_base->uart_clk_ctrl, 0);
 387         zynq_clk_register_periph_clk(&clks[uart1_clk],
 388                                      &slcr_base->uart_clk_ctrl, 0);
 389
 390         zynq_clk_register_periph_clk(&clks[dbg_trc_clk],
 391                                      &slcr_base->dbg_clk_ctrl, 0);
 392         zynq_clk_register_periph_clk(&clks[dbg_apb_clk],
 393                                      &slcr_base->dbg_clk_ctrl, 0);
 394
 395         zynq_clk_register_periph_clk(&clks[pcap_clk],
 396                                      &slcr_base->pcap_clk_ctrl, 0);
 397
 398         zynq_clk_register_periph_clk(&clks[fclk0_clk],
 399                                      &slcr_base->fpga0_clk_ctrl, 1);
 400         zynq_clk_register_periph_clk(&clks[fclk1_clk],
 401                                      &slcr_base->fpga1_clk_ctrl, 1);
 402         zynq_clk_register_periph_clk(&clks[fclk2_clk],
 403                                      &slcr_base->fpga2_clk_ctrl, 1);
 404         zynq_clk_register_periph_clk(&clks[fclk3_clk],
 405                                      &slcr_base->fpga3_clk_ctrl, 1);
 406 }
 407
 408 /**
 409  * zynq_clk_register_aper_clk() - Set up a APER clock with the framework
 410  * @clk:        Pointer to struct clk for the clock
 411  * @ctrl:       Clock control register
 412  */
 413 static void zynq_clk_register_aper_clk(struct clk *clk, u32 *ctrl)
 414 {
 415         clk->reg = ctrl;
 416         clk->parent = cpu_1x_clk;
 417         clk->frequency = zynq_clk_get_rate(clk->parent);
 418 }
 419
 420 static void init_aper_clocks(void)
 421 {
 422         zynq_clk_register_aper_clk(&clks[usb0_aper_clk],
 423                                    &slcr_base->aper_clk_ctrl);
 424         zynq_clk_register_aper_clk(&clks[usb1_aper_clk],
 425                                    &slcr_base->aper_clk_ctrl);
 426
 427         zynq_clk_register_aper_clk(&clks[gem0_aper_clk],
 428                                    &slcr_base->aper_clk_ctrl);
 429         zynq_clk_register_aper_clk(&clks[gem1_aper_clk],
 430                                    &slcr_base->aper_clk_ctrl);
 431
 432         zynq_clk_register_aper_clk(&clks[sdio0_aper_clk],
 433                                    &slcr_base->aper_clk_ctrl);
 434         zynq_clk_register_aper_clk(&clks[sdio1_aper_clk],
 435                                    &slcr_base->aper_clk_ctrl);
 436
 437         zynq_clk_register_aper_clk(&clks[spi0_aper_clk],
 438                                    &slcr_base->aper_clk_ctrl);
 439         zynq_clk_register_aper_clk(&clks[spi1_aper_clk],
 440                                    &slcr_base->aper_clk_ctrl);
 441
 442         zynq_clk_register_aper_clk(&clks[can0_aper_clk],
 443                                    &slcr_base->aper_clk_ctrl);
 444         zynq_clk_register_aper_clk(&clks[can1_aper_clk],
 445                                    &slcr_base->aper_clk_ctrl);
 446
 447         zynq_clk_register_aper_clk(&clks[i2c0_aper_clk],
 448                                    &slcr_base->aper_clk_ctrl);
 449         zynq_clk_register_aper_clk(&clks[i2c1_aper_clk],
 450                                    &slcr_base->aper_clk_ctrl);
 451
 452         zynq_clk_register_aper_clk(&clks[uart0_aper_clk],
 453                                    &slcr_base->aper_clk_ctrl);
 454         zynq_clk_register_aper_clk(&clks[uart1_aper_clk],
 455                                    &slcr_base->aper_clk_ctrl);
 456
 457         zynq_clk_register_aper_clk(&clks[gpio_aper_clk],
 458                                    &slcr_base->aper_clk_ctrl);
 459
 460         zynq_clk_register_aper_clk(&clks[lqspi_aper_clk],
 461                                    &slcr_base->aper_clk_ctrl);
 462
 463         zynq_clk_register_aper_clk(&clks[smc_aper_clk],
 464                                    &slcr_base->aper_clk_ctrl);
 465 }
 466
 467 /**
 468  * __zynq_clk_pll_get_rate() - Get PLL rate
 469  * @addr:       Address of the PLL's control register
 470  * Returns the current PLL output rate.
 471  */
 472 static unsigned long __zynq_clk_pll_get_rate(u32 *addr)
 473 {
 474         u32 reg, mul, bypass;
 475
 476         reg = readl(addr);
 477         bypass = reg & PLLCTRL_BPFORCE_MASK;
 478         if (bypass)
 479                 mul = 1;
 480         else
 481                 mul = (reg & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;
 482
 483         return CONFIG_ZYNQ_PS_CLK_FREQ * mul;
 484 }
 485
 486 /**
 487  * zynq_clk_pll_get_rate() - Get PLL rate
 488  * @pll:        Handle of the PLL
 489  * Returns the current clock rate of @pll.
 490  */
 491 static unsigned long zynq_clk_pll_get_rate(struct clk *pll)
 492 {
 493         return __zynq_clk_pll_get_rate(pll->reg);
 494 }
 495
 496 /**
 497  * zynq_clk_register_pll() - Set up a PLL with the framework
 498  * @clk:        Pointer to struct clk for the PLL
 499  * @ctrl:       PLL control register
 500  * @prate:      PLL input clock rate
 501  */
 502 static void zynq_clk_register_pll(struct clk *clk, u32 *ctrl,
 503                 unsigned long prate)
 504 {
 505         clk->reg = ctrl;
 506         clk->frequency = zynq_clk_pll_get_rate(clk);
 507         clk->ops.get_rate = zynq_clk_pll_get_rate;
 508 }
 509
 510 /**
 511  * clkid_2_register() - Get clock control register
 512  * @id: Clock identifier of one of the PLLs
 513  * Returns the address of the requested PLL's control register.
 514  */
 515 static u32 *clkid_2_register(enum zynq_clk id)
 516 {
 517         switch (id) {
 518         case armpll_clk:
 519                 return &slcr_base->arm_pll_ctrl;
 520         case ddrpll_clk:
 521                 return &slcr_base->ddr_pll_ctrl;
 522         case iopll_clk:
 523                 return &slcr_base->io_pll_ctrl;
 524         default:
 525                 return &slcr_base->io_pll_ctrl;
 526         }
 527 }
 528
 529 /* API */
 530 /**
 531  * zynq_clk_early_init() - Early init for the clock framework
 532  *
 533  * This function is called from before relocation and sets up the CPU clock
 534  * frequency in the global data struct.
 535  */
 536 void zynq_clk_early_init(void)
 537 {
 538         u32 reg = readl(&slcr_base->arm_clk_ctrl);
 539         u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 540         u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
 541         enum zynq_clk parent = __zynq_clk_cpu_get_parent(srcsel);
 542         u32 *pllreg = clkid_2_register(parent);
 543         unsigned long prate = __zynq_clk_pll_get_rate(pllreg);
 544
 545         if (!div)
 546                 div = 1;
 547
 548         gd->cpu_clk = DIV_ROUND_CLOSEST(prate, div);
 549 }
 550
 551 /**
 552  * get_uart_clk() - Get UART input frequency
 553  * @dev_index:  UART ID
 554  * Returns UART input clock frequency in Hz.
 555  *
 556  * Compared to zynq_clk_get_rate() this function is designed to work before
 557  * relocation and can be called when the serial UART is set up.
 558  */
 559 unsigned long get_uart_clk(int dev_index)
 560 {
 561         u32 reg = readl(&slcr_base->uart_clk_ctrl);
 562         u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 563         u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
 564         enum zynq_clk parent = __zynq_clk_periph_get_parent(srcsel);
 565         u32 *pllreg = clkid_2_register(parent);
 566         unsigned long prate = __zynq_clk_pll_get_rate(pllreg);
 567
 568         if (!div)
 569                 div = 1;
 570
 571         return DIV_ROUND_CLOSEST(prate, div);
 572 }
 573
 574 /**
 575  * set_cpu_clk_info() - Initialize clock framework
 576  * Always returns zero.
 577  *
 578  * This function is called from common code after relocation and sets up the
 579  * clock framework. The framework must not be used before this function had been
 580  * called.
 581  */
 582 int set_cpu_clk_info(void)
 583 {
 584         zynq_clk_register_pll(&clks[armpll_clk], &slcr_base->arm_pll_ctrl,
 585                               CONFIG_ZYNQ_PS_CLK_FREQ);
 586         zynq_clk_register_pll(&clks[ddrpll_clk], &slcr_base->ddr_pll_ctrl,
 587                               CONFIG_ZYNQ_PS_CLK_FREQ);
 588         zynq_clk_register_pll(&clks[iopll_clk], &slcr_base->io_pll_ctrl,
 589                               CONFIG_ZYNQ_PS_CLK_FREQ);
 590
 591         init_ddr_clocks();
 592         init_cpu_clocks();
 593         init_periph_clocks();
 594         init_aper_clocks();
 595
 596         gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
 597         gd->bd->bi_dsp_freq = 0;
 598
 599         return 0;
 600 }
 601
 602 /**
 603  * zynq_clk_get_rate() - Get clock rate
 604  * @clk:        Clock identifier
 605  * Returns the current clock rate of @clk on success or zero for an invalid
 606  * clock id.
 607  */
 608 unsigned long zynq_clk_get_rate(enum zynq_clk clk)
 609 {
 610         if (clk < 0 || clk >= clk_max)
 611                 return 0;
 612
 613         return clks[clk].frequency;
 614 }
 615
 616 /**
 617  * zynq_clk_set_rate() - Set clock rate
 618  * @clk:        Clock identifier
 619  * @rate:       Requested clock rate
 620  * Passes on the return value from the clock's set_rate() function or negative
 621  * errno.
 622  */
 623 int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate)
 624 {
 625         if (clk < 0 || clk >= clk_max)
 626                 return -ENODEV;
 627
 628         if (clks[clk].ops.set_rate)
 629                 return clks[clk].ops.set_rate(&clks[clk], rate);
 630
 631         return -ENXIO;
 632 }
 633
 634 /**
 635  * zynq_clk_get_name() - Get clock name
 636  * @clk:        Clock identifier
 637  * Returns the name of @clk.
 638  */
 639 const char *zynq_clk_get_name(enum zynq_clk clk)
 640 {
 641         return clk_names[clk];
 642 }
 643
 644 /**
 645  * soc_clk_dump() - Print clock frequencies
 646  * Returns zero on success
 647  *
 648  * Implementation for the clk dump command.
 649  */
 650 int soc_clk_dump(void)
 651 {
 652         int i;
 653
 654         printf("clk\t\tfrequency\n");
 655         for (i = 0; i < clk_max; i++) {
 656                 const char *name = zynq_clk_get_name(i);
 657                 if (name)
 658                         printf("%10s%20lu\n", name, zynq_clk_get_rate(i));
 659         }
 660
 661         return 0;
 662 }