2 * Copyright (C) Marvell International Ltd. and its affiliates
3 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/soc.h>
12 #define UBOOT_CNTR 0 /* counter to use for U-Boot timer */
15 * ARM Timers Registers Map
17 #define CNTMR_CTRL_REG &tmr_regs->ctrl
18 #define CNTMR_RELOAD_REG(tmrnum) &tmr_regs->tmr[tmrnum].reload
19 #define CNTMR_VAL_REG(tmrnum) &tmr_regs->tmr[tmrnum].val
22 * ARM Timers Control Register
23 * CPU_TIMERS_CTRL_REG (CTCR)
25 #define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
26 #define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
28 #define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
29 #define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
31 /* Only Armada XP have the 25MHz enable bit (Kirkwood doesn't) */
32 #if defined(CONFIG_ARMADA_XP)
33 #define CTCR_ARM_TIMER_25MHZ_OFFS(cntr) (cntr + 11)
34 #define CTCR_ARM_TIMER_25MHZ(cntr) (1 << CTCR_ARM_TIMER_25MHZ_OFFS(cntr))
36 #define CTCR_ARM_TIMER_25MHZ(cntr) 0
39 #define TIMER_LOAD_VAL 0xffffffff
41 #define timestamp gd->arch.tbl
42 #define lastdec gd->arch.lastinc
44 /* Timer reload and current value registers */
46 u32 reload; /* Timer reload reg */
47 u32 val; /* Timer value reg */
51 struct kwtmr_registers {
52 u32 ctrl; /* Timer control reg */
54 struct kwtmr_val tmr[4];
59 DECLARE_GLOBAL_DATA_PTR;
61 static struct kwtmr_registers *tmr_regs =
62 (struct kwtmr_registers *)MVEBU_TIMER_BASE;
64 static inline ulong read_timer(void)
66 return readl(CNTMR_VAL_REG(UBOOT_CNTR)) / (CONFIG_SYS_TCLK / 1000);
69 ulong get_timer_masked(void)
71 ulong now = read_timer();
75 timestamp += lastdec - now;
77 /* we have an overflow ... */
78 timestamp += lastdec +
79 (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
86 ulong get_timer(ulong base)
88 return get_timer_masked() - base;
91 void __udelay(unsigned long usec)
96 current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
97 delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
99 if (current < delayticks) {
100 delayticks -= current;
101 while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ;
102 while ((TIMER_LOAD_VAL - delayticks) <
103 readl(CNTMR_VAL_REG(UBOOT_CNTR))) ;
105 while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
106 (current - delayticks)) ;
115 /* load value into timer */
116 writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
117 writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
119 /* enable timer in auto reload mode */
120 clrsetbits_le32(CNTMR_CTRL_REG, CTCR_ARM_TIMER_25MHZ(UBOOT_CNTR),
121 CTCR_ARM_TIMER_EN(UBOOT_CNTR) |
122 CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR));
124 /* init the timestamp and lastdec value */
125 lastdec = read_timer();
132 * This function is derived from PowerPC code (read timebase as long long).
133 * On ARM it just returns the timer value.
135 unsigned long long get_ticks(void)
141 * This function is derived from PowerPC code (timebase clock frequency).
142 * On ARM it returns the number of timer ticks per second.
144 ulong get_tbclk (void)
146 return (ulong)CONFIG_SYS_HZ;