2 * Copyright (C) Marvell International Ltd. and its affiliates
3 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/kirkwood.h>
12 #define UBOOT_CNTR 0 /* counter to use for uboot timer */
14 /* Timer reload and current value registers */
16 u32 reload; /* Timer reload reg */
17 u32 val; /* Timer value reg */
21 struct kwtmr_registers {
22 u32 ctrl; /* Timer control reg */
24 struct kwtmr_val tmr[2];
29 struct kwtmr_registers *kwtmr_regs = (struct kwtmr_registers *)KW_TIMER_BASE;
32 * ARM Timers Registers Map
34 #define CNTMR_CTRL_REG &kwtmr_regs->ctrl
35 #define CNTMR_RELOAD_REG(tmrnum) &kwtmr_regs->tmr[tmrnum].reload
36 #define CNTMR_VAL_REG(tmrnum) &kwtmr_regs->tmr[tmrnum].val
39 * ARM Timers Control Register
40 * CPU_TIMERS_CTRL_REG (CTCR)
42 #define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
43 #define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS)
44 #define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
45 #define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
47 #define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
48 #define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1)
49 #define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
50 #define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
53 * ARM Timer\Watchdog Reload Register
54 * CNTMR_RELOAD_REG (TRR)
56 #define TRG_ARM_TIMER_REL_OFFS 0
57 #define TRG_ARM_TIMER_REL_MASK 0xffffffff
60 * ARM Timer\Watchdog Register
61 * CNTMR_VAL_REG (TVRG)
63 #define TVR_ARM_TIMER_OFFS 0
64 #define TVR_ARM_TIMER_MASK 0xffffffff
65 #define TVR_ARM_TIMER_MAX 0xffffffff
66 #define TIMER_LOAD_VAL 0xffffffff
68 #define READ_TIMER (readl(CNTMR_VAL_REG(UBOOT_CNTR)) / \
69 (CONFIG_SYS_TCLK / 1000))
71 DECLARE_GLOBAL_DATA_PTR;
73 #define timestamp gd->arch.tbl
74 #define lastdec gd->arch.lastinc
76 ulong get_timer_masked(void)
78 ulong now = READ_TIMER;
82 timestamp += lastdec - now;
84 /* we have an overflow ... */
85 timestamp += lastdec +
86 (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
93 ulong get_timer(ulong base)
95 return get_timer_masked() - base;
98 void __udelay(unsigned long usec)
103 current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
104 delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
106 if (current < delayticks) {
107 delayticks -= current;
108 while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ;
109 while ((TIMER_LOAD_VAL - delayticks) <
110 readl(CNTMR_VAL_REG(UBOOT_CNTR))) ;
112 while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
113 (current - delayticks)) ;
122 unsigned int cntmrctrl;
124 /* load value into timer */
125 writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
126 writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
128 /* enable timer in auto reload mode */
129 cntmrctrl = readl(CNTMR_CTRL_REG);
130 cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
131 cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
132 writel(cntmrctrl, CNTMR_CTRL_REG);
134 /* init the timestamp and lastdec value */
135 lastdec = READ_TIMER;
142 * This function is derived from PowerPC code (read timebase as long long).
143 * On ARM it just returns the timer value.
145 unsigned long long get_ticks(void)
151 * This function is derived from PowerPC code (timebase clock frequency).
152 * On ARM it returns the number of timer ticks per second.
154 ulong get_tbclk (void)
156 return (ulong)CONFIG_SYS_HZ;