2 * Copyright (C) 2005-2006 Atmel Corporation
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/sdram.h>
27 #include <asm/arch/clk.h>
28 #include <asm/arch/hardware.h>
32 unsigned long sdram_init(void *sdram_base, const struct sdram_config *config)
34 unsigned long sdram_size;
38 cfgreg = (HSDRAMC1_BF(NC, config->col_bits - 8)
39 | HSDRAMC1_BF(NR, config->row_bits - 11)
40 | HSDRAMC1_BF(NB, config->bank_bits - 1)
41 | HSDRAMC1_BF(CAS, config->cas)
42 | HSDRAMC1_BF(TWR, config->twr)
43 | HSDRAMC1_BF(TRC, config->trc)
44 | HSDRAMC1_BF(TRP, config->trp)
45 | HSDRAMC1_BF(TRCD, config->trcd)
46 | HSDRAMC1_BF(TRAS, config->tras)
47 | HSDRAMC1_BF(TXSR, config->txsr));
49 if (config->data_bits == SDRAM_DATA_16BIT)
50 cfgreg |= HSDRAMC1_BIT(DBW);
52 hsdramc1_writel(CR, cfgreg);
54 /* Send a NOP to turn on the clock (necessary on some chips) */
55 hsdramc1_writel(MR, HSDRAMC1_MODE_NOP);
57 writel(0, sdram_base);
60 * Initialization sequence for SDRAM, from the data sheet:
62 * 1. A minimum pause of 200 us is provided to precede any
68 * 2. A Precharge All command is issued to the SDRAM
70 hsdramc1_writel(MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
72 writel(0, sdram_base);
75 * 3. Eight auto-refresh (CBR) cycles are provided
77 hsdramc1_writel(MR, HSDRAMC1_MODE_AUTO_REFRESH);
79 for (i = 0; i < 8; i++)
80 writel(0, sdram_base);
83 * 4. A mode register set (MRS) cycle is issued to program
84 * SDRAM parameters, in particular CAS latency and burst
87 * The address will be chosen by the SDRAMC automatically; we
88 * just have to make sure BA[1:0] are set to 0.
90 hsdramc1_writel(MR, HSDRAMC1_MODE_LOAD_MODE);
92 writel(0, sdram_base);
95 * 5. The application must go into Normal Mode, setting Mode
96 * to 0 in the Mode Register and performing a write access
97 * at any location in the SDRAM.
99 hsdramc1_writel(MR, HSDRAMC1_MODE_NORMAL);
101 writel(0, sdram_base);
104 * 6. Write refresh rate into SDRAMC refresh timer count
105 * register (refresh rate = timing between refresh cycles).
107 hsdramc1_writel(TR, config->refresh_period);
109 if (config->data_bits == SDRAM_DATA_16BIT)
110 sdram_size = 1 << (config->row_bits + config->col_bits
111 + config->bank_bits + 1);
113 sdram_size = 1 << (config->row_bits + config->col_bits
114 + config->bank_bits + 2);