2 * Copyright (C) 2005-2006 Atmel Corporation
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clk.h>
12 #include <asm/arch/hardware.h>
16 unsigned long sdram_init(void *sdram_base, const struct sdram_config *config)
18 unsigned long sdram_size;
22 cfgreg = (HSDRAMC1_BF(NC, config->col_bits - 8)
23 | HSDRAMC1_BF(NR, config->row_bits - 11)
24 | HSDRAMC1_BF(NB, config->bank_bits - 1)
25 | HSDRAMC1_BF(CAS, config->cas)
26 | HSDRAMC1_BF(TWR, config->twr)
27 | HSDRAMC1_BF(TRC, config->trc)
28 | HSDRAMC1_BF(TRP, config->trp)
29 | HSDRAMC1_BF(TRCD, config->trcd)
30 | HSDRAMC1_BF(TRAS, config->tras)
31 | HSDRAMC1_BF(TXSR, config->txsr));
33 if (config->data_bits == SDRAM_DATA_16BIT)
34 cfgreg |= HSDRAMC1_BIT(DBW);
36 hsdramc1_writel(CR, cfgreg);
38 /* Send a NOP to turn on the clock (necessary on some chips) */
39 hsdramc1_writel(MR, HSDRAMC1_MODE_NOP);
41 writel(0, sdram_base);
44 * Initialization sequence for SDRAM, from the data sheet:
46 * 1. A minimum pause of 200 us is provided to precede any
52 * 2. A Precharge All command is issued to the SDRAM
54 hsdramc1_writel(MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
56 writel(0, sdram_base);
59 * 3. Eight auto-refresh (CBR) cycles are provided
61 hsdramc1_writel(MR, HSDRAMC1_MODE_AUTO_REFRESH);
63 for (i = 0; i < 8; i++)
64 writel(0, sdram_base);
67 * 4. A mode register set (MRS) cycle is issued to program
68 * SDRAM parameters, in particular CAS latency and burst
71 * The address will be chosen by the SDRAMC automatically; we
72 * just have to make sure BA[1:0] are set to 0.
74 hsdramc1_writel(MR, HSDRAMC1_MODE_LOAD_MODE);
76 writel(0, sdram_base);
79 * 5. The application must go into Normal Mode, setting Mode
80 * to 0 in the Mode Register and performing a write access
81 * at any location in the SDRAM.
83 hsdramc1_writel(MR, HSDRAMC1_MODE_NORMAL);
85 writel(0, sdram_base);
88 * 6. Write refresh rate into SDRAMC refresh timer count
89 * register (refresh rate = timing between refresh cycles).
91 hsdramc1_writel(TR, config->refresh_period);
93 if (config->data_bits == SDRAM_DATA_16BIT)
94 sdram_size = 1 << (config->row_bits + config->col_bits
95 + config->bank_bits + 1);
97 sdram_size = 1 << (config->row_bits + config->col_bits
98 + config->bank_bits + 2);