2 * Copyright (C) 2005-2008 Atmel Corporation
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/ptrace.h>
24 #include <asm/sysreg.h>
26 #define SYSREG_MMUCR_I_OFFSET 2
27 #define SYSREG_MMUCR_S_OFFSET 4
29 #define SR_INIT (SYSREG_BIT(GM) | SYSREG_BIT(EM) | SYSREG_BIT(M0))
30 /* due to errata (unreliable branch folding) clear FE bit explicitly */
31 #define CPUCR_INIT ((SYSREG_BIT(BI) | SYSREG_BIT(BE) \
32 | SYSREG_BIT(RE) | SYSREG_BIT(IBE) \
33 | SYSREG_BIT(IEE)) & ~SYSREG_BIT(FE))
36 * To save some space, we use the same entry point for
37 * exceptions and reset. This avoids lots of alignment padding
38 * since the reset vector is always suitably aligned.
40 .section .exception.text, "ax", @progbits
43 .type _start, @function
44 .type _evba, @function
49 rjmp unknown_exception /* Unrecoverable exception */
51 rjmp unknown_exception /* TLB multiple hit */
53 rjmp unknown_exception /* Bus error data fetch */
55 rjmp unknown_exception /* Bus error instruction fetch */
57 rjmp unknown_exception /* NMI */
59 rjmp unknown_exception /* Instruction address */
61 rjmp unknown_exception /* ITLB protection */
63 rjmp unknown_exception /* Breakpoint */
65 rjmp unknown_exception /* Illegal opcode */
67 rjmp unknown_exception /* Unimplemented instruction */
69 rjmp unknown_exception /* Privilege violation */
71 rjmp unknown_exception /* Floating-point */
73 rjmp unknown_exception /* Coprocessor absent */
75 rjmp unknown_exception /* Data Address (read) */
77 rjmp unknown_exception /* Data Address (write) */
79 rjmp unknown_exception /* DTLB Protection (read) */
81 rjmp unknown_exception /* DTLB Protection (write) */
83 rjmp unknown_exception /* DTLB Modified */
85 .org 0x50 /* ITLB Miss */
88 .org 0x60 /* DTLB Miss (read) */
91 .org 0x70 /* DTLB Miss (write) */
94 rcall mmu_handle_tlb_miss
96 brne unknown_exception
99 .size _evba, . - _evba
102 .type unknown_exception, @function
104 /* Figure out whether we're handling an exception (Exception
105 * mode) or just booting (Supervisor mode). */
106 csrfcz SYSREG_M1_OFFSET
107 brcc at32ap_cpu_bootstrap
109 /* This is an exception. Complain. */
111 sub r8, sp, REG_R12 - REG_R0 - 4
113 mfsr r10, SYSREG_RAR_EX
114 mfsr r11, SYSREG_RSR_EX
118 rcall do_unknown_exception
121 /* The COUNT/COMPARE timer interrupt handler */
122 .global timer_interrupt_handler
123 .type timer_interrupt_handler,@function
125 timer_interrupt_handler:
127 * Increment timer_overflow and re-write COMPARE with 0xffffffff.
129 * We're running at interrupt level 3, so we don't need to save
130 * r8-r12 or lr to the stack.
132 lda.w r8, timer_overflow
135 mtsr SYSREG_COMPARE, r10
141 * CPU bootstrap after reset is handled here. SoC code may
142 * override this in case they need to initialize oscillators,
145 .section .text.at32ap_cpu_bootstrap, "ax", @progbits
146 .global at32ap_cpu_bootstrap
147 .weak at32ap_cpu_bootstrap
148 .type at32ap_cpu_bootstrap, @function
150 at32ap_cpu_bootstrap:
151 /* Reset the Status Register */
156 /* Reset CPUCR and invalidate the BTB */
158 mtsr SYSREG_CPUCR, r2
160 /* Flush the caches */
166 /* Reset the MMU to default settings */
167 mov r0, SYSREG_BIT(MMUCR_S) | SYSREG_BIT(MMUCR_I)
168 mtsr SYSREG_MMUCR, r0
170 /* Internal RAM should not need any initialization. We might
171 have to initialize external RAM here if the part doesn't
172 have internal RAM (or we may use the data cache) */
174 /* Jump to cacheable segment */
178 1: .long at32ap_low_level_init
179 .size _start, . - _start
181 /* Common CPU bootstrap code after oscillator/cache/etc. init */
182 .section .text.avr32ap_low_level_init, "ax", @progbits
183 .global at32ap_low_level_init
184 .type at32ap_low_level_init, @function
186 at32ap_low_level_init:
189 /* Initialize the GOT pointer */
197 .type sp_init,@object
199 .long CONFIG_SYS_INIT_SP_ADDR
201 .long 3b - _GLOBAL_OFFSET_TABLE_
204 * void relocate_code(new_sp, new_gd, monitor_addr)
206 * Relocate the u-boot image into RAM and continue from there.
209 .section .text.relocate_code,"ax",@progbits
210 .global relocate_code
211 .type relocate_code,@function
213 mov sp, r12 /* use new stack */
214 mov r12, r11 /* save new_gd */
215 mov r11, r10 /* save destination address */
217 /* copy .text section and flush the cache along the way */
220 sub lr, r10, r8 /* relocation offset */
229 cache r10[-4], 0x0d /* dcache clean/invalidate */
230 cache r10[-4], 0x01 /* icache invalidate */
233 /* flush write buffer */
236 /* copy data sections */
253 sub r0, pc, . - in_ram
258 /* find the new GOT and relocate it */
259 lddpc r6, got_init_reloc
271 /* Move the exception handlers */
276 /* Do the rest of the initialization sequence */
281 .long 3b - _GLOBAL_OFFSET_TABLE_
283 .size relocate_code, . - relocate_code