2 * Copyright (C) 2006 Atmel Corporation
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef __ASM_AVR32_ARCH_CLK_H__
7 #define __ASM_AVR32_ARCH_CLK_H__
9 #include <asm/arch/chip-features.h>
10 #include <asm/arch/portmux.h>
13 #define PLL0_RATE ((CONFIG_SYS_OSC0_HZ / CONFIG_SYS_PLL0_DIV) \
14 * CONFIG_SYS_PLL0_MUL)
15 #define MAIN_CLK_RATE PLL0_RATE
17 #define MAIN_CLK_RATE (CONFIG_SYS_OSC0_HZ)
20 static inline unsigned long get_cpu_clk_rate(void)
22 return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_CPU;
24 static inline unsigned long get_hsb_clk_rate(void)
26 return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB;
28 static inline unsigned long get_pba_clk_rate(void)
30 return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBA;
32 static inline unsigned long get_pbb_clk_rate(void)
34 return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBB;
37 /* Accessors for specific devices. More will be added as needed. */
38 static inline unsigned long get_sdram_clk_rate(void)
40 return get_hsb_clk_rate();
42 #ifdef AT32AP700x_CHIP_HAS_USART
43 static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
45 return get_pba_clk_rate();
48 #ifdef AT32AP700x_CHIP_HAS_MACB
49 static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
51 return get_pbb_clk_rate();
53 static inline unsigned long get_macb_hclk_rate(unsigned int dev_id)
55 return get_hsb_clk_rate();
58 #ifdef AT32AP700x_CHIP_HAS_MMCI
59 static inline unsigned long get_mci_clk_rate(void)
61 return get_pbb_clk_rate();
64 #ifdef AT32AP700x_CHIP_HAS_SPI
65 static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
67 return get_pba_clk_rate();
70 #ifdef AT32AP700x_CHIP_HAS_LCDC
71 static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
73 return get_hsb_clk_rate();
77 extern void clk_init(void);
79 /* Board code may need the SDRAM base clock as a compile-time constant */
80 #define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB)
82 /* Generic clock control */
90 /* Some generic clocks have specific roles */
91 #define GCLK_DAC_SAMPLE_CLK 6
92 #define GCLK_LCDC_PIXCLK 7
94 extern unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent,
95 unsigned long rate, unsigned long parent_rate);
98 * gclk_set_rate - configure and enable a generic clock
99 * @id: Which GCLK[id] to enable
100 * @parent: Parent clock feeding the GCLK
101 * @rate: Target rate of the GCLK in Hz
103 * Returns the actual GCLK rate in Hz, after rounding to the nearest
106 * All three parameters are usually constant, hence the inline.
108 static inline unsigned long gclk_set_rate(unsigned int id,
109 enum gclk_parent parent, unsigned long rate)
111 unsigned long parent_rate;
117 case GCLK_PARENT_OSC0:
118 parent_rate = CONFIG_SYS_OSC0_HZ;
120 #ifdef CONFIG_SYS_OSC1_HZ
121 case GCLK_PARENT_OSC1:
122 parent_rate = CONFIG_SYS_OSC1_HZ;
126 case GCLK_PARENT_PLL0:
127 parent_rate = PLL0_RATE;
131 case GCLK_PARENT_PLL1:
132 parent_rate = PLL1_RATE;
140 return __gclk_set_rate(id, parent, rate, parent_rate);
144 * gclk_enable_output - enable output on a GCLK pin
145 * @id: Which GCLK[id] pin to enable
146 * @drive_strength: Drive strength of external GCLK pin, if applicable
148 static inline void gclk_enable_output(unsigned int id,
149 unsigned long drive_strength)
153 portmux_select_peripheral(PORTMUX_PORT_A, 1 << 30,
154 PORTMUX_FUNC_A, drive_strength);
157 portmux_select_peripheral(PORTMUX_PORT_A, 1 << 31,
158 PORTMUX_FUNC_A, drive_strength);
161 portmux_select_peripheral(PORTMUX_PORT_B, 1 << 19,
162 PORTMUX_FUNC_A, drive_strength);
165 portmux_select_peripheral(PORTMUX_PORT_B, 1 << 29,
166 PORTMUX_FUNC_A, drive_strength);
169 portmux_select_peripheral(PORTMUX_PORT_B, 1 << 30,
170 PORTMUX_FUNC_A, drive_strength);
175 #endif /* __ASM_AVR32_ARCH_CLK_H__ */