2 * Copyright (C) 2006 Atmel Corporation
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 #ifndef __ASM_AVR32_ARCH_CLK_H__
23 #define __ASM_AVR32_ARCH_CLK_H__
25 #include <asm/arch/chip-features.h>
26 #include <asm/arch/portmux.h>
29 #define PLL0_RATE ((CONFIG_SYS_OSC0_HZ / CONFIG_SYS_PLL0_DIV) \
30 * CONFIG_SYS_PLL0_MUL)
31 #define MAIN_CLK_RATE PLL0_RATE
33 #define MAIN_CLK_RATE (CONFIG_SYS_OSC0_HZ)
36 static inline unsigned long get_cpu_clk_rate(void)
38 return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_CPU;
40 static inline unsigned long get_hsb_clk_rate(void)
42 return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB;
44 static inline unsigned long get_pba_clk_rate(void)
46 return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBA;
48 static inline unsigned long get_pbb_clk_rate(void)
50 return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBB;
53 /* Accessors for specific devices. More will be added as needed. */
54 static inline unsigned long get_sdram_clk_rate(void)
56 return get_hsb_clk_rate();
58 #ifdef AT32AP700x_CHIP_HAS_USART
59 static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
61 return get_pba_clk_rate();
64 #ifdef AT32AP700x_CHIP_HAS_MACB
65 static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
67 return get_pbb_clk_rate();
69 static inline unsigned long get_macb_hclk_rate(unsigned int dev_id)
71 return get_hsb_clk_rate();
74 #ifdef AT32AP700x_CHIP_HAS_MMCI
75 static inline unsigned long get_mci_clk_rate(void)
77 return get_pbb_clk_rate();
80 #ifdef AT32AP700x_CHIP_HAS_SPI
81 static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
83 return get_pba_clk_rate();
86 #ifdef AT32AP700x_CHIP_HAS_LCDC
87 static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
89 return get_hsb_clk_rate();
93 extern void clk_init(void);
95 /* Board code may need the SDRAM base clock as a compile-time constant */
96 #define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB)
98 /* Generic clock control */
100 GCLK_PARENT_OSC0 = 0,
101 GCLK_PARENT_OSC1 = 1,
102 GCLK_PARENT_PLL0 = 2,
103 GCLK_PARENT_PLL1 = 3,
106 /* Some generic clocks have specific roles */
107 #define GCLK_DAC_SAMPLE_CLK 6
108 #define GCLK_LCDC_PIXCLK 7
110 extern unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent,
111 unsigned long rate, unsigned long parent_rate);
114 * gclk_set_rate - configure and enable a generic clock
115 * @id: Which GCLK[id] to enable
116 * @parent: Parent clock feeding the GCLK
117 * @rate: Target rate of the GCLK in Hz
119 * Returns the actual GCLK rate in Hz, after rounding to the nearest
122 * All three parameters are usually constant, hence the inline.
124 static inline unsigned long gclk_set_rate(unsigned int id,
125 enum gclk_parent parent, unsigned long rate)
127 unsigned long parent_rate;
133 case GCLK_PARENT_OSC0:
134 parent_rate = CONFIG_SYS_OSC0_HZ;
136 #ifdef CONFIG_SYS_OSC1_HZ
137 case GCLK_PARENT_OSC1:
138 parent_rate = CONFIG_SYS_OSC1_HZ;
142 case GCLK_PARENT_PLL0:
143 parent_rate = PLL0_RATE;
147 case GCLK_PARENT_PLL1:
148 parent_rate = PLL1_RATE;
156 return __gclk_set_rate(id, parent, rate, parent_rate);
160 * gclk_enable_output - enable output on a GCLK pin
161 * @id: Which GCLK[id] pin to enable
162 * @drive_strength: Drive strength of external GCLK pin, if applicable
164 static inline void gclk_enable_output(unsigned int id,
165 unsigned long drive_strength)
169 portmux_select_peripheral(PORTMUX_PORT_A, 1 << 30,
170 PORTMUX_FUNC_A, drive_strength);
173 portmux_select_peripheral(PORTMUX_PORT_A, 1 << 31,
174 PORTMUX_FUNC_A, drive_strength);
177 portmux_select_peripheral(PORTMUX_PORT_B, 1 << 19,
178 PORTMUX_FUNC_A, drive_strength);
181 portmux_select_peripheral(PORTMUX_PORT_B, 1 << 29,
182 PORTMUX_FUNC_A, drive_strength);
185 portmux_select_peripheral(PORTMUX_PORT_B, 1 << 30,
186 PORTMUX_FUNC_A, drive_strength);
191 #endif /* __ASM_AVR32_ARCH_CLK_H__ */