2 * Blackfin cache control code
4 * Copyright 2003-2008 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #include <asm/linkage.h>
13 #include <asm/blackfin.h>
16 /* Since all L1 caches work the same way, we use the same method for flushing
17 * them. Only the actual flush instruction differs. We write this in asm as
18 * GCC can be hard to coax into writing nice hardware loops.
20 * Also, we assume the following register setup:
24 .macro do_flush flushins:req optflushins optnopins label
28 /* start = (start & -L1_CACHE_BYTES) */
31 /* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */
36 /* count = (end - start) >> L1_CACHE_SHIFT */
38 R2 >>= L1_CACHE_SHIFT;
45 LSETUP (1f, 2f) LC1 = P1;
65 /* Invalidate all instruction cache lines assocoiated with this memory area */
66 ENTRY(_blackfin_icache_flush_range)
67 do_flush IFLUSH, , nop
68 ENDPROC(_blackfin_icache_flush_range)
70 /* Flush all cache lines assocoiated with this area of memory. */
71 ENTRY(_blackfin_icache_dcache_flush_range)
72 do_flush FLUSH, IFLUSH
73 ENDPROC(_blackfin_icache_dcache_flush_range)
75 /* Throw away all D-cached data in specified region without any obligation to
76 * write them back. Since the Blackfin ISA does not have an "invalidate"
77 * instruction, we use flush/invalidate. Perhaps as a speed optimization we
78 * could bang on the DTEST MMRs ...
80 ENTRY(_blackfin_dcache_flush_invalidate_range)
82 ENDPROC(_blackfin_dcache_flush_invalidate_range)
84 /* Flush all data cache lines assocoiated with this memory area */
85 ENTRY(_blackfin_dcache_flush_range)
86 do_flush FLUSH, , , .Ldfr
87 ENDPROC(_blackfin_dcache_flush_range)