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Blackfin: set up simple NMI handlers for anomaly 05000219
[u-boot] / arch / blackfin / cpu / cpu.c
1 /*
2  * U-boot - cpu.c CPU specific functions
3  *
4  * Copyright (c) 2005-2008 Analog Devices Inc.
5  *
6  * (C) Copyright 2000-2004
7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8  *
9  * Licensed under the GPL-2 or later.
10  */
11
12 #include <common.h>
13 #include <command.h>
14 #include <asm/blackfin.h>
15 #include <asm/cplb.h>
16 #include <asm/mach-common/bits/core.h>
17 #include <asm/mach-common/bits/ebiu.h>
18 #include <asm/mach-common/bits/trace.h>
19
20 #include "cpu.h"
21 #include "serial.h"
22
23 ulong bfin_poweron_retx;
24
25 __attribute__ ((__noreturn__))
26 void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
27 {
28 #ifndef CONFIG_BFIN_BOOTROM_USES_EVT1
29         /* Build a NOP slide over the LDR jump block.  Whee! */
30         char nops[0xC];
31         serial_early_puts("NOP Slide\n");
32         memset(nops, 0x00, sizeof(nops));
33         memcpy((void *)L1_INST_SRAM, nops, sizeof(nops));
34 #endif
35
36         if (!loaded_from_ldr) {
37                 /* Relocate sections into L1 if the LDR didn't do it -- don't
38                  * check length because the linker script does the size
39                  * checking at build time.
40                  */
41                 serial_early_puts("L1 Relocate\n");
42                 extern char _stext_l1[], _text_l1_lma[], _text_l1_len[];
43                 memcpy(&_stext_l1, &_text_l1_lma, (unsigned long)_text_l1_len);
44                 extern char _sdata_l1[], _data_l1_lma[], _data_l1_len[];
45                 memcpy(&_sdata_l1, &_data_l1_lma, (unsigned long)_data_l1_len);
46         }
47 #if defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
48         /* The BF537 bootrom will reset the EBIU_AMGCTL register on us
49          * after it has finished loading the LDR.  So configure it again.
50          */
51         else
52                 bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
53 #endif
54
55         /* Save RETX so we can pass it while booting Linux */
56         bfin_poweron_retx = bootflag;
57
58 #ifdef CONFIG_DEBUG_DUMP
59         /* Turn on hardware trace buffer */
60         bfin_write_TBUFCTL(TBUFPWR | TBUFEN);
61 #endif
62
63 #ifndef CONFIG_PANIC_HANG
64         /* Reset upon a double exception rather than just hanging.
65          * Do not do bfin_read on SWRST as that will reset status bits.
66          */
67         bfin_write_SWRST(DOUBLE_FAULT);
68 #endif
69
70         serial_early_puts("Board init flash\n");
71         board_init_f(bootflag);
72 }
73
74 int exception_init(void)
75 {
76         bfin_write_EVT3(trap);
77         return 0;
78 }
79
80 int irq_init(void)
81 {
82 #ifdef SIC_IMASK0
83         bfin_write_SIC_IMASK0(0);
84         bfin_write_SIC_IMASK1(0);
85 # ifdef SIC_IMASK2
86         bfin_write_SIC_IMASK2(0);
87 # endif
88 #elif defined(SICA_IMASK0)
89         bfin_write_SICA_IMASK0(0);
90         bfin_write_SICA_IMASK1(0);
91 #else
92         bfin_write_SIC_IMASK(0);
93 #endif
94         /* Set up a dummy NMI handler if needed.  */
95         if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS || ANOMALY_05000219)
96                 bfin_write_EVT2(evt_nmi);       /* NMI */
97         bfin_write_EVT5(evt_default);   /* hardware error */
98         bfin_write_EVT6(evt_default);   /* core timer */
99         bfin_write_EVT7(evt_default);
100         bfin_write_EVT8(evt_default);
101         bfin_write_EVT9(evt_default);
102         bfin_write_EVT10(evt_default);
103         bfin_write_EVT11(evt_default);
104         bfin_write_EVT12(evt_default);
105         bfin_write_EVT13(evt_default);
106         bfin_write_EVT14(evt_default);
107         bfin_write_EVT15(evt_default);
108         bfin_write_ILAT(0);
109         CSYNC();
110         /* enable hardware error irq */
111         irq_flags = 0x3f;
112         local_irq_enable();
113         return 0;
114 }