2 * U-boot - cpu.c CPU specific functions
4 * Copyright (c) 2005-2008 Analog Devices Inc.
6 * (C) Copyright 2000-2004
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * Licensed under the GPL-2 or later.
14 #include <asm/blackfin.h>
16 #include <asm/mach-common/bits/core.h>
17 #include <asm/mach-common/bits/ebiu.h>
18 #include <asm/mach-common/bits/trace.h>
23 ulong bfin_poweron_retx;
25 __attribute__ ((__noreturn__))
26 void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
28 #ifndef CONFIG_BFIN_BOOTROM_USES_EVT1
29 /* Build a NOP slide over the LDR jump block. Whee! */
31 serial_early_puts("NOP Slide\n");
32 memset(nops, 0x00, sizeof(nops));
33 memcpy((void *)L1_INST_SRAM, nops, sizeof(nops));
36 if (!loaded_from_ldr) {
37 /* Relocate sections into L1 if the LDR didn't do it -- don't
38 * check length because the linker script does the size
39 * checking at build time.
41 serial_early_puts("L1 Relocate\n");
42 extern char _stext_l1[], _text_l1_lma[], _text_l1_len[];
43 memcpy(&_stext_l1, &_text_l1_lma, (unsigned long)_text_l1_len);
44 extern char _sdata_l1[], _data_l1_lma[], _data_l1_len[];
45 memcpy(&_sdata_l1, &_data_l1_lma, (unsigned long)_data_l1_len);
47 #if defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
48 /* The BF537 bootrom will reset the EBIU_AMGCTL register on us
49 * after it has finished loading the LDR. So configure it again.
52 bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
55 /* Save RETX so we can pass it while booting Linux */
56 bfin_poweron_retx = bootflag;
58 #ifdef CONFIG_DEBUG_DUMP
59 /* Turn on hardware trace buffer */
60 bfin_write_TBUFCTL(TBUFPWR | TBUFEN);
63 #ifndef CONFIG_PANIC_HANG
64 /* Reset upon a double exception rather than just hanging.
65 * Do not do bfin_read on SWRST as that will reset status bits.
67 bfin_write_SWRST(DOUBLE_FAULT);
70 serial_early_puts("Board init flash\n");
71 board_init_f(bootflag);
74 int exception_init(void)
76 bfin_write_EVT3(trap);
83 bfin_write_SIC_IMASK0(0);
84 bfin_write_SIC_IMASK1(0);
86 bfin_write_SIC_IMASK2(0);
88 #elif defined(SICA_IMASK0)
89 bfin_write_SICA_IMASK0(0);
90 bfin_write_SICA_IMASK1(0);
92 bfin_write_SIC_IMASK(0);
94 /* Set up a dummy NMI handler if needed. */
95 if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS || ANOMALY_05000219)
96 bfin_write_EVT2(evt_nmi); /* NMI */
97 bfin_write_EVT5(evt_default); /* hardware error */
98 bfin_write_EVT6(evt_default); /* core timer */
99 bfin_write_EVT7(evt_default);
100 bfin_write_EVT8(evt_default);
101 bfin_write_EVT9(evt_default);
102 bfin_write_EVT10(evt_default);
103 bfin_write_EVT11(evt_default);
104 bfin_write_EVT12(evt_default);
105 bfin_write_EVT13(evt_default);
106 bfin_write_EVT14(evt_default);
107 bfin_write_EVT15(evt_default);
110 /* enable hardware error irq */