2 * U-boot - cpu.c CPU specific functions
4 * Copyright (c) 2005-2008 Analog Devices Inc.
6 * (C) Copyright 2000-2004
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * Licensed under the GPL-2 or later.
18 #include <asm/blackfin.h>
20 #include <asm/clock.h>
21 #include <asm/mach-common/bits/core.h>
22 #include <asm/mach-common/bits/ebiu.h>
23 #include <asm/mach-common/bits/trace.h>
28 ulong bfin_poweron_retx;
29 DECLARE_GLOBAL_DATA_PTR;
31 #if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START)
32 void bfin_core1_start(void)
36 bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020);
39 bfin_write32(RCU0_SVECT1, COREB_L1_CODE_START);
40 bfin_write32(RCU0_CRCTL, 0);
42 bfin_write32(RCU0_CRCTL, 0x2);
44 /* Check if core 1 starts */
45 while (!(bfin_read32(RCU0_CRSTAT) & 0x2))
48 bfin_write32(RCU0_CRCTL, 0);
50 /* flag to notify cces core 1 application */
51 bfin_write32(SDU0_MSG_SET, (1 << 19));
56 __attribute__((always_inline))
57 static inline void serial_early_puts(const char *s)
59 #ifdef CONFIG_DEBUG_EARLY_SERIAL
60 serial_puts("Early: ");
65 static int global_board_data_init(void)
67 #ifndef CONFIG_SYS_GBL_DATA_ADDR
68 # define CONFIG_SYS_GBL_DATA_ADDR 0
70 #ifndef CONFIG_SYS_BD_INFO_ADDR
71 # define CONFIG_SYS_BD_INFO_ADDR 0
76 if (CONFIG_SYS_GBL_DATA_ADDR) {
77 gd = (gd_t *)(CONFIG_SYS_GBL_DATA_ADDR);
78 memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
83 if (CONFIG_SYS_BD_INFO_ADDR) {
84 bd = (bd_t *)(CONFIG_SYS_BD_INFO_ADDR);
85 memset(bd, 0, GENERATED_BD_INFO_SIZE);
93 bd->bi_r_version = version_string;
94 bd->bi_cpu = __stringify(CONFIG_BFIN_CPU);
95 bd->bi_board_name = CONFIG_SYS_BOARD;
96 bd->bi_vco = get_vco();
97 bd->bi_cclk = get_cclk();
98 bd->bi_sclk = get_sclk();
99 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
100 bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
102 gd->ram_size = CONFIG_SYS_MAX_RAM_SIZE;
107 static void display_global_data(void)
111 #ifndef CONFIG_DEBUG_EARLY_SERIAL
116 printf(" gd: %p\n", gd);
117 printf(" |-flags: %lx\n", gd->flags);
118 printf(" |-board_type: %lx\n", gd->arch.board_type);
119 printf(" |-baudrate: %u\n", gd->baudrate);
120 printf(" |-have_console: %lx\n", gd->have_console);
121 printf(" |-ram_size: %lx\n", gd->ram_size);
122 printf(" |-env_addr: %lx\n", gd->env_addr);
123 printf(" |-env_valid: %lx\n", gd->env_valid);
124 printf(" |-jt(%p): %p\n", gd->jt, *(gd->jt));
125 printf(" \\-bd: %p\n", gd->bd);
126 printf(" |-bi_boot_params: %lx\n", bd->bi_boot_params);
127 printf(" |-bi_memstart: %lx\n", bd->bi_memstart);
128 printf(" |-bi_memsize: %lx\n", bd->bi_memsize);
129 printf(" |-bi_flashstart: %lx\n", bd->bi_flashstart);
130 printf(" |-bi_flashsize: %lx\n", bd->bi_flashsize);
131 printf(" \\-bi_flashoffset: %lx\n", bd->bi_flashoffset);
134 #define CPLB_PAGE_SIZE (4 * 1024 * 1024)
135 #define CPLB_PAGE_MASK (~(CPLB_PAGE_SIZE - 1))
136 #if defined(__ADSPBF60x__)
137 #define CPLB_EX_PAGE_SIZE (16 * 1024 * 1024)
138 #define CPLB_EX_PAGE_MASK (~(CPLB_EX_PAGE_SIZE - 1))
140 #define CPLB_EX_PAGE_SIZE CPLB_PAGE_SIZE
141 #define CPLB_EX_PAGE_MASK CPLB_PAGE_MASK
143 void init_cplbtables(void)
145 uint32_t *ICPLB_ADDR, *ICPLB_DATA;
146 uint32_t *DCPLB_ADDR, *DCPLB_DATA;
147 uint32_t extern_memory;
150 void icplb_add(uint32_t addr, uint32_t data)
152 bfin_write32(ICPLB_ADDR + i, addr);
153 bfin_write32(ICPLB_DATA + i, data);
155 void dcplb_add(uint32_t addr, uint32_t data)
157 bfin_write32(DCPLB_ADDR + i, addr);
158 bfin_write32(DCPLB_DATA + i, data);
161 /* populate a few common entries ... we'll let
162 * the memory map and cplb exception handler do
163 * the rest of the work.
166 ICPLB_ADDR = (uint32_t *)ICPLB_ADDR0;
167 ICPLB_DATA = (uint32_t *)ICPLB_DATA0;
168 DCPLB_ADDR = (uint32_t *)DCPLB_ADDR0;
169 DCPLB_DATA = (uint32_t *)DCPLB_DATA0;
171 icplb_add(0xFFA00000, L1_IMEMORY);
172 dcplb_add(0xFF800000, L1_DMEMORY);
174 #if defined(__ADSPBF60x__)
176 dcplb_add(CONFIG_SYS_FLASH_BASE, PAGE_SIZE_16MB | CPLB_DIRTY |
177 CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID);
181 if (CONFIG_MEM_SIZE) {
182 uint32_t mbase = CONFIG_SYS_MONITOR_BASE;
183 uint32_t mend = mbase + CONFIG_SYS_MONITOR_LEN - 1;
184 mbase &= CPLB_PAGE_MASK;
185 mend &= CPLB_PAGE_MASK;
187 icplb_add(mbase, SDRAM_IKERNEL);
188 dcplb_add(mbase, SDRAM_DKERNEL);
192 * If the monitor crosses a 4 meg boundary, we'll need
193 * to lock two entries for it. We assume it doesn't
194 * cross two 4 meg boundaries ...
197 icplb_add(mend, SDRAM_IKERNEL);
198 dcplb_add(mend, SDRAM_DKERNEL);
203 #ifndef __ADSPBF60x__
204 icplb_add(0x20000000, SDRAM_INON_CHBL);
205 dcplb_add(0x20000000, SDRAM_EBIU);
209 /* Add entries for the rest of external RAM up to the bootrom */
212 #ifdef CONFIG_DEBUG_NULL_PTR
213 icplb_add(extern_memory,
214 (SDRAM_IKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB);
215 dcplb_add(extern_memory,
216 (SDRAM_DKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB);
218 icplb_add(extern_memory, SDRAM_IKERNEL);
219 dcplb_add(extern_memory, SDRAM_DKERNEL);
220 extern_memory += CPLB_PAGE_SIZE;
224 while (i < 16 && extern_memory <
225 (CONFIG_SYS_MONITOR_BASE & CPLB_EX_PAGE_MASK)) {
226 icplb_add(extern_memory, SDRAM_IGENERIC);
227 dcplb_add(extern_memory, SDRAM_DGENERIC);
228 extern_memory += CPLB_EX_PAGE_SIZE;
238 int print_cpuinfo(void)
242 printf("CPU: ADSP %s (Detected Rev: 0.%d) (%s boot)\n",
245 get_bfin_boot_mode(CONFIG_BFIN_BOOT_MODE));
247 printf("Clock: VCO: %s MHz, ", strmhz(buf, get_vco()));
248 printf("Core: %s MHz, ", strmhz(buf, get_cclk()));
249 #if defined(__ADSPBF60x__)
250 printf("System0: %s MHz, ", strmhz(buf, get_sclk0()));
251 printf("System1: %s MHz, ", strmhz(buf, get_sclk1()));
252 printf("Dclk: %s MHz\n", strmhz(buf, get_dclk()));
254 printf("System: %s MHz\n", strmhz(buf, get_sclk()));
260 int exception_init(void)
262 bfin_write_EVT3(trap);
269 bfin_write_SIC_IMASK0(0);
270 bfin_write_SIC_IMASK1(0);
272 bfin_write_SIC_IMASK2(0);
274 #elif defined(SICA_IMASK0)
275 bfin_write_SICA_IMASK0(0);
276 bfin_write_SICA_IMASK1(0);
277 #elif defined(SIC_IMASK)
278 bfin_write_SIC_IMASK(0);
280 /* Set up a dummy NMI handler if needed. */
281 if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS || ANOMALY_05000219)
282 bfin_write_EVT2(evt_nmi); /* NMI */
283 bfin_write_EVT5(evt_default); /* hardware error */
284 bfin_write_EVT6(evt_default); /* core timer */
285 bfin_write_EVT7(evt_default);
286 bfin_write_EVT8(evt_default);
287 bfin_write_EVT9(evt_default);
288 bfin_write_EVT10(evt_default);
289 bfin_write_EVT11(evt_default);
290 bfin_write_EVT12(evt_default);
291 bfin_write_EVT13(evt_default);
292 bfin_write_EVT14(evt_default);
293 bfin_write_EVT15(evt_default);
296 /* enable hardware error irq */
302 __attribute__ ((__noreturn__))
303 void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
305 #ifndef CONFIG_BFIN_BOOTROM_USES_EVT1
306 /* Build a NOP slide over the LDR jump block. Whee! */
308 serial_early_puts("NOP Slide\n");
309 memset(nops, 0x00, sizeof(nops));
310 memcpy((void *)L1_INST_SRAM, nops, sizeof(nops));
313 if (!loaded_from_ldr) {
314 /* Relocate sections into L1 if the LDR didn't do it -- don't
315 * check length because the linker script does the size
316 * checking at build time.
318 serial_early_puts("L1 Relocate\n");
319 extern char _stext_l1[], _text_l1_lma[], _text_l1_len[];
320 memcpy(&_stext_l1, &_text_l1_lma, (unsigned long)_text_l1_len);
321 extern char _sdata_l1[], _data_l1_lma[], _data_l1_len[];
322 memcpy(&_sdata_l1, &_data_l1_lma, (unsigned long)_data_l1_len);
326 * Make sure our async settings are committed. Some bootroms
327 * (like the BF537) will reset some registers on us after it
328 * has finished loading the LDR. Or if we're booting over
329 * JTAG, the initcode never got a chance to run. Or if we
330 * aren't booting from parallel flash, the initcode skipped
331 * this step completely.
333 program_async_controller(NULL);
335 /* Save RETX so we can pass it while booting Linux */
336 bfin_poweron_retx = bootflag;
338 #ifdef CONFIG_DEBUG_DUMP
339 /* Turn on hardware trace buffer */
340 bfin_write_TBUFCTL(TBUFPWR | TBUFEN);
343 #ifndef CONFIG_PANIC_HANG
344 /* Reset upon a double exception rather than just hanging.
345 * Do not do bfin_read on SWRST as that will reset status bits.
348 bfin_write_SWRST(DOUBLE_FAULT);
352 #if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START)
356 serial_early_puts("Init global data\n");
357 global_board_data_init();
361 /* should not be reached */
365 int arch_cpu_init(void)
367 serial_early_puts("Init CPLB tables\n");
370 serial_early_puts("Exceptions setup\n");
373 #ifndef CONFIG_ICACHE_OFF
374 serial_early_puts("Turn on ICACHE\n");
377 #ifndef CONFIG_DCACHE_OFF
378 serial_early_puts("Turn on DCACHE\n");
383 if (GENERATED_GBL_DATA_SIZE < sizeof(*gd))
388 serial_early_puts("IRQ init\n");
394 int arch_misc_init(void)
396 #if defined(CONFIG_SYS_I2C)
400 display_global_data();
402 if (CONFIG_MEM_SIZE && bfin_os_log_check()) {
403 puts("\nLog buffer from operating system:\n");
411 int interrupt_init(void)