2 * U-boot - cpu.c CPU specific functions
4 * Copyright (c) 2005-2008 Analog Devices Inc.
6 * (C) Copyright 2000-2004
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * Licensed under the GPL-2 or later.
14 #include <asm/blackfin.h>
16 #include <asm/mach-common/bits/core.h>
17 #include <asm/mach-common/bits/ebiu.h>
18 #include <asm/mach-common/bits/trace.h>
24 ulong bfin_poweron_retx;
26 void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
28 #ifndef CONFIG_BFIN_BOOTROM_USES_EVT1
29 /* Build a NOP slide over the LDR jump block. Whee! */
31 serial_early_puts("NOP Slide\n");
32 memset(nops, 0x00, sizeof(nops));
33 memcpy((void *)L1_INST_SRAM, nops, sizeof(nops));
36 if (!loaded_from_ldr) {
37 /* Relocate sections into L1 if the LDR didn't do it -- don't
38 * check length because the linker script does the size
39 * checking at build time.
41 serial_early_puts("L1 Relocate\n");
42 extern char _stext_l1[], _text_l1_lma[], _text_l1_len[];
43 memcpy(&_stext_l1, &_text_l1_lma, (unsigned long)_text_l1_len);
44 extern char _sdata_l1[], _data_l1_lma[], _data_l1_len[];
45 memcpy(&_sdata_l1, &_data_l1_lma, (unsigned long)_data_l1_len);
49 * Make sure our async settings are committed. Some bootroms
50 * (like the BF537) will reset some registers on us after it
51 * has finished loading the LDR. Or if we're booting over
52 * JTAG, the initcode never got a chance to run. Or if we
53 * aren't booting from parallel flash, the initcode skipped
54 * this step completely.
56 program_async_controller(NULL);
58 /* Save RETX so we can pass it while booting Linux */
59 bfin_poweron_retx = bootflag;
61 #ifdef CONFIG_DEBUG_DUMP
62 /* Turn on hardware trace buffer */
63 bfin_write_TBUFCTL(TBUFPWR | TBUFEN);
66 #ifndef CONFIG_PANIC_HANG
67 /* Reset upon a double exception rather than just hanging.
68 * Do not do bfin_read on SWRST as that will reset status bits.
71 bfin_write_SWRST(DOUBLE_FAULT);
75 serial_early_puts("Board init flash\n");
76 board_init_f(bootflag);
79 int exception_init(void)
81 bfin_write_EVT3(trap);
88 bfin_write_SIC_IMASK0(0);
89 bfin_write_SIC_IMASK1(0);
91 bfin_write_SIC_IMASK2(0);
93 #elif defined(SICA_IMASK0)
94 bfin_write_SICA_IMASK0(0);
95 bfin_write_SICA_IMASK1(0);
96 #elif defined(SIC_IMASK)
97 bfin_write_SIC_IMASK(0);
99 /* Set up a dummy NMI handler if needed. */
100 if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS || ANOMALY_05000219)
101 bfin_write_EVT2(evt_nmi); /* NMI */
102 bfin_write_EVT5(evt_default); /* hardware error */
103 bfin_write_EVT6(evt_default); /* core timer */
104 bfin_write_EVT7(evt_default);
105 bfin_write_EVT8(evt_default);
106 bfin_write_EVT9(evt_default);
107 bfin_write_EVT10(evt_default);
108 bfin_write_EVT11(evt_default);
109 bfin_write_EVT12(evt_default);
110 bfin_write_EVT13(evt_default);
111 bfin_write_EVT14(evt_default);
112 bfin_write_EVT15(evt_default);
115 /* enable hardware error irq */