2 * initcode.c - Initialize the processor. This is usually entails things
3 * like external memory, voltage regulators, etc... Note that this file
4 * cannot make any function calls as it may be executed all by itself by
5 * the Blackfin's bootrom in LDR format.
7 * Copyright (c) 2004-2008 Analog Devices Inc.
9 * Licensed under the GPL-2 or later.
12 #define BFIN_IN_INITCODE
15 #include <asm/blackfin.h>
16 #include <asm/mach-common/bits/bootrom.h>
17 #include <asm/mach-common/bits/core.h>
18 #include <asm/mach-common/bits/ebiu.h>
19 #include <asm/mach-common/bits/pll.h>
20 #include <asm/mach-common/bits/uart.h>
24 __attribute__((always_inline))
25 static inline void serial_init(void)
27 uint32_t uart_base = UART_DLL;
30 # ifdef BFIN_BOOT_UART_USE_RTS
31 # define BFIN_UART_USE_RTS 1
33 # define BFIN_UART_USE_RTS 0
35 if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
38 /* force RTS rather than relying on auto RTS */
39 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL);
41 /* Wait for the line to clear up. We cannot rely on UART
42 * registers as none of them reflect the status of the RSR.
43 * Instead, we'll sleep for ~10 bit times at 9600 baud.
44 * We can precalc things here by assuming boot values for
45 * PLL rather than loading registers and calculating.
46 * baud = SCLK / (16 ^ (1 - EDBO) * Divisor)
48 * Divisor = (SCLK / baud) / 16
49 * SCLK = baud * 16 * Divisor
50 * SCLK = (0x14 * CONFIG_CLKIN_HZ) / 5
51 * CCLK = (16 * Divisor * 5) * (9600 / 10)
52 * In reality, this will probably be just about 1 second delay,
53 * so assuming 9600 baud is OK (both as a very low and too high
54 * speed as this will buffer things enough).
56 #define _NUMBITS (10) /* how many bits to delay */
57 #define _LOWBAUD (9600) /* low baud rate */
58 #define _SCLK ((0x14 * CONFIG_CLKIN_HZ) / 5) /* SCLK based on PLL */
59 #define _DIVISOR ((_SCLK / _LOWBAUD) / 16) /* UART DLL/DLH */
60 #define _NUMINS (3) /* how many instructions in loop */
61 #define _CCLK (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS)
64 asm volatile("" : : : "memory");
68 if (BFIN_DEBUG_EARLY_SERIAL) {
69 int ucen = bfin_read16(&pUART->gctl) & UCEN;
70 serial_early_init(uart_base);
72 /* If the UART is off, that means we need to program
73 * the baud rate ourselves initially.
76 serial_early_set_baud(uart_base, CONFIG_BAUDRATE);
80 __attribute__((always_inline))
81 static inline void serial_deinit(void)
84 uint32_t uart_base = UART_DLL;
86 if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
87 /* clear forced RTS rather than relying on auto RTS */
88 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL);
93 __attribute__((always_inline))
94 static inline void serial_putc(char c)
96 uint32_t uart_base = UART_DLL;
98 if (!BFIN_DEBUG_EARLY_SERIAL)
104 bfin_write16(&pUART->thr, c);
106 while (!(bfin_read16(&pUART->lsr) & TEMT))
110 __attribute__((always_inline)) static inline void
111 program_nmi_handler(void)
115 /* Older bootroms don't create a dummy NMI handler,
116 * so make one ourselves ASAP in case it fires.
118 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS && !ANOMALY_05000219)
122 "%0 = RETS;" /* Save current RETS */
123 "CALL 1f;" /* Figure out current PC */
124 "RTN;" /* The simple NMI handler */
126 "%1 = RETS;" /* Load addr of NMI handler */
127 "RETS = %0;" /* Restore RETS */
128 "[%2] = %1;" /* Write NMI handler */
129 : "=r"(tmp1), "=r"(tmp2) : "ab"(EVT2)
133 /* Max SCLK can be 133MHz ... dividing that by (2*4) gives
134 * us a freq of 16MHz for SPI which should generally be
135 * slow enough for the slow reads the bootrom uses.
137 #if !defined(CONFIG_SPI_FLASH_SLOW_READ) && \
138 ((defined(__ADSPBF52x__) && __SILICON_REVISION__ >= 2) || \
139 (defined(__ADSPBF54x__) && __SILICON_REVISION__ >= 1))
140 # define BOOTROM_SUPPORTS_SPI_FAST_READ 1
142 # define BOOTROM_SUPPORTS_SPI_FAST_READ 0
144 #ifndef CONFIG_SPI_BAUD_INITBLOCK
145 # define CONFIG_SPI_BAUD_INITBLOCK (BOOTROM_SUPPORTS_SPI_FAST_READ ? 2 : 4)
148 # define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD
151 /* PLL_DIV defines */
152 #ifndef CONFIG_PLL_DIV_VAL
153 # if (CONFIG_CCLK_DIV == 1)
154 # define CONFIG_CCLK_ACT_DIV CCLK_DIV1
155 # elif (CONFIG_CCLK_DIV == 2)
156 # define CONFIG_CCLK_ACT_DIV CCLK_DIV2
157 # elif (CONFIG_CCLK_DIV == 4)
158 # define CONFIG_CCLK_ACT_DIV CCLK_DIV4
159 # elif (CONFIG_CCLK_DIV == 8)
160 # define CONFIG_CCLK_ACT_DIV CCLK_DIV8
162 # define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
164 # define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV)
167 #ifndef CONFIG_PLL_LOCKCNT_VAL
168 # define CONFIG_PLL_LOCKCNT_VAL 0x0300
171 #ifndef CONFIG_PLL_CTL_VAL
172 # define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF)
175 #ifndef CONFIG_EBIU_RSTCTL_VAL
176 # define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
178 #if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0)
179 # error invalid EBIU_RSTCTL value: must not set reserved bits
182 #ifndef CONFIG_EBIU_MBSCTL_VAL
183 # define CONFIG_EBIU_MBSCTL_VAL 0
186 #if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0)
187 # error invalid EBIU_DDRQUE value: must not set reserved bits
190 /* Make sure our voltage value is sane so we don't blow up! */
191 #ifndef CONFIG_VR_CTL_VAL
192 # define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
193 # if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__)
194 # define CCLK_VLEV_120 400000000
195 # define CCLK_VLEV_125 533000000
196 # elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
197 # define CCLK_VLEV_120 401000000
198 # define CCLK_VLEV_125 401000000
199 # elif defined(__ADSPBF561__)
200 # define CCLK_VLEV_120 300000000
201 # define CCLK_VLEV_125 501000000
203 # if BFIN_CCLK < CCLK_VLEV_120
204 # define CONFIG_VR_CTL_VLEV VLEV_120
205 # elif BFIN_CCLK < CCLK_VLEV_125
206 # define CONFIG_VR_CTL_VLEV VLEV_125
208 # define CONFIG_VR_CTL_VLEV VLEV_130
210 # if defined(__ADSPBF52x__) /* TBD; use default */
211 # undef CONFIG_VR_CTL_VLEV
212 # define CONFIG_VR_CTL_VLEV VLEV_110
213 # elif defined(__ADSPBF54x__) /* TBD; use default */
214 # undef CONFIG_VR_CTL_VLEV
215 # define CONFIG_VR_CTL_VLEV VLEV_120
216 # elif defined(__ADSPBF538__) || defined(__ADSPBF539__) /* TBD; use default */
217 # undef CONFIG_VR_CTL_VLEV
218 # define CONFIG_VR_CTL_VLEV VLEV_125
221 # ifdef CONFIG_BFIN_MAC
222 # define CONFIG_VR_CTL_CLKBUF CLKBUFOE
224 # define CONFIG_VR_CTL_CLKBUF 0
227 # if defined(__ADSPBF52x__)
228 # define CONFIG_VR_CTL_FREQ FREQ_1000
230 # define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000)
233 # define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
236 /* some parts do not have an on-chip voltage regulator */
237 #if defined(__ADSPBF51x__)
238 # define CONFIG_HAS_VR 0
239 # undef CONFIG_VR_CTL_VAL
240 # define CONFIG_VR_CTL_VAL 0
242 # define CONFIG_HAS_VR 1
247 /* Blackfin with SDRAM */
248 #ifndef CONFIG_EBIU_SDBCTL_VAL
249 # if CONFIG_MEM_SIZE == 16
250 # define CONFIG_EBSZ_VAL EBSZ_16
251 # elif CONFIG_MEM_SIZE == 32
252 # define CONFIG_EBSZ_VAL EBSZ_32
253 # elif CONFIG_MEM_SIZE == 64
254 # define CONFIG_EBSZ_VAL EBSZ_64
255 # elif CONFIG_MEM_SIZE == 128
256 # define CONFIG_EBSZ_VAL EBSZ_128
257 # elif CONFIG_MEM_SIZE == 256
258 # define CONFIG_EBSZ_VAL EBSZ_256
259 # elif CONFIG_MEM_SIZE == 512
260 # define CONFIG_EBSZ_VAL EBSZ_512
262 # error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_SIZE
264 # if CONFIG_MEM_ADD_WDTH == 8
265 # define CONFIG_EBCAW_VAL EBCAW_8
266 # elif CONFIG_MEM_ADD_WDTH == 9
267 # define CONFIG_EBCAW_VAL EBCAW_9
268 # elif CONFIG_MEM_ADD_WDTH == 10
269 # define CONFIG_EBCAW_VAL EBCAW_10
270 # elif CONFIG_MEM_ADD_WDTH == 11
271 # define CONFIG_EBCAW_VAL EBCAW_11
273 # error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_ADD_WDTH
275 # define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE)
280 /* Conflicting Column Address Widths Causes SDRAM Errors:
281 * EB2CAW and EB3CAW must be the same
284 # if ((CONFIG_EBIU_SDBCTL_VAL & 0x30000000) >> 8) != (CONFIG_EBIU_SDBCTL_VAL & 0x00300000)
285 # error "Anomaly 05000362: EB2CAW and EB3CAW must be the same"
289 __attribute__((always_inline)) static inline void
290 program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
294 /* Save the clock pieces that are used in baud rate calculation */
295 if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
297 *sdivB = bfin_read_PLL_DIV() & 0xf;
298 *vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
299 *divB = serial_early_get_div();
305 #ifdef CONFIG_HW_WATCHDOG
306 # ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
307 # define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
309 /* Program the watchdog with an initial timeout of ~20 seconds.
310 * Hopefully that should be long enough to load the u-boot LDR
311 * (from wherever) and then the common u-boot code can take over.
312 * In bypass mode, the start.S would have already set a much lower
313 * timeout, so don't clobber that.
315 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
317 bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
318 bfin_write_WDOG_CTL(0);
325 /* Blackfin bootroms use the SPI slow read opcode instead of the SPI
326 * fast read, so we need to slow down the SPI clock a lot more during
327 * boot. Once we switch over to u-boot's SPI flash driver, we'll
328 * increase the speed appropriately.
330 if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
332 if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4)
333 bs->dFlags |= BFLAG_FASTREAD;
334 bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
341 __attribute__((always_inline)) static inline bool
342 maybe_self_refresh(ADI_BOOT_DATA *bs)
346 if (!CONFIG_MEM_SIZE)
349 /* If external memory is enabled, put it into self refresh first. */
350 #if defined(EBIU_RSTCTL)
351 if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
353 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ);
356 #elif defined(EBIU_SDGCTL)
357 if (bfin_read_EBIU_SDBCTL() & EBE) {
359 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
369 __attribute__((always_inline)) static inline u16
370 program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
376 vr_ctl = bfin_read_VR_CTL();
380 /* If we're entering self refresh, make sure it has happened. */
382 #if defined(EBIU_RSTCTL)
383 while (!(bfin_read_EBIU_RSTCTL() & SRACK))
385 #elif defined(EBIU_SDGCTL)
386 while (!(bfin_read_EBIU_SDSTAT() & SDSRA))
394 /* With newer bootroms, we use the helper function to set up
395 * the memory controller. Older bootroms lacks such helpers
396 * so we do it ourselves.
398 if (!ANOMALY_05000386) {
401 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
402 ADI_SYSCTRL_VALUES memory_settings;
403 uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_LOCKCNT;
404 if (!ANOMALY_05000440)
405 actions |= SYSCTRL_PLLDIV;
407 actions |= SYSCTRL_VRCTL;
408 if (CONFIG_VR_CTL_VAL & FREQ_MASK)
409 actions |= SYSCTRL_INTVOLTAGE;
411 actions |= SYSCTRL_EXTVOLTAGE;
412 memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
414 actions |= SYSCTRL_EXTVOLTAGE;
415 memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
416 memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
417 memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
419 bfin_write_SIC_IWR1(0);
422 bfrom_SysControl(actions, &memory_settings, NULL);
424 if (ANOMALY_05000440)
425 bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
427 bfin_write_SIC_IWR1(-1);
430 bfin_write_SICA_IWR0(-1);
431 bfin_write_SICA_IWR1(-1);
437 /* Disable all peripheral wakeups except for the PLL event. */
439 bfin_write_SIC_IWR0(1);
440 bfin_write_SIC_IWR1(0);
442 bfin_write_SIC_IWR2(0);
444 #elif defined(SICA_IWR0)
445 bfin_write_SICA_IWR0(1);
446 bfin_write_SICA_IWR1(0);
448 bfin_write_SIC_IWR(1);
453 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
454 bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
458 /* Only reprogram when needed to avoid triggering unnecessary
459 * PLL relock sequences.
461 if (vr_ctl != CONFIG_VR_CTL_VAL) {
463 bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
470 bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
474 /* Only reprogram when needed to avoid triggering unnecessary
475 * PLL relock sequences.
477 if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
479 bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
486 /* Restore all peripheral wakeups. */
488 bfin_write_SIC_IWR0(-1);
489 bfin_write_SIC_IWR1(-1);
491 bfin_write_SIC_IWR2(-1);
493 #elif defined(SICA_IWR0)
494 bfin_write_SICA_IWR0(-1);
495 bfin_write_SICA_IWR1(-1);
497 bfin_write_SIC_IWR(-1);
508 __attribute__((always_inline)) static inline void
509 update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
513 /* Since we've changed the SCLK above, we may need to update
514 * the UART divisors (UART baud rates are based on SCLK).
515 * Do the division by hand as there are no native instructions
516 * for dividing which means we'd generate a libgcc reference.
518 if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
520 unsigned int sdivR, vcoR;
521 sdivR = bfin_read_PLL_DIV() & 0xf;
522 vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
523 int dividend = sdivB * divB * vcoR;
524 int divisor = vcoB * sdivR;
525 unsigned int quotient;
526 for (quotient = 0; dividend > 0; ++quotient)
528 serial_early_put_div(UART_DLL, quotient - ANOMALY_05000230);
535 __attribute__((always_inline)) static inline void
536 program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
540 if (!CONFIG_MEM_SIZE)
545 /* Program the external memory controller before we come out of
546 * self-refresh. This only works with our SDRAM controller.
549 # ifdef CONFIG_EBIU_SDRRC_VAL
550 bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
552 # ifdef CONFIG_EBIU_SDBCTL_VAL
553 bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
555 # ifdef CONFIG_EBIU_SDGCTL_VAL
556 bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
562 /* Now that we've reprogrammed, take things out of self refresh. */
564 #if defined(EBIU_RSTCTL)
565 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
566 #elif defined(EBIU_SDGCTL)
567 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS));
572 /* Our DDR controller sucks and cannot be programmed while in
573 * self-refresh. So we have to pull it out before programming.
576 # ifdef CONFIG_EBIU_RSTCTL_VAL
577 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
579 # ifdef CONFIG_EBIU_DDRCTL0_VAL
580 bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
582 # ifdef CONFIG_EBIU_DDRCTL1_VAL
583 bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
585 # ifdef CONFIG_EBIU_DDRCTL2_VAL
586 bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
588 # ifdef CONFIG_EBIU_DDRCTL3_VAL
589 /* default is disable, so don't need to force this */
590 bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
592 # ifdef CONFIG_EBIU_DDRQUE_VAL
593 bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | CONFIG_EBIU_DDRQUE_VAL);
600 __attribute__((always_inline)) static inline void
601 check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs)
605 if (!CONFIG_MEM_SIZE)
610 /* Are we coming out of hibernate (suspend to memory) ?
611 * The memory layout is:
612 * 0x0: hibernate magic for anomaly 307 (0xDEADBEEF)
613 * 0x4: return address
616 * SCKELOW is unreliable on older parts (anomaly 307)
618 if (ANOMALY_05000307 || vr_ctl & 0x8000) {
619 uint32_t *hibernate_magic = 0;
620 __builtin_bfin_ssync(); /* make sure memory controller is done */
621 if (hibernate_magic[0] == 0xDEADBEEF) {
623 bfin_write_EVT15(hibernate_magic[1]);
624 bfin_write_IMASK(EVT_IVG15);
625 __asm__ __volatile__ (
626 /* load reti early to avoid anomaly 281 */
628 /* clear hibernate magic */
630 /* load stack pointer */
632 /* lower ourselves from reset ivg to ivg15 */
636 : "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */)
645 __attribute__((always_inline)) static inline void
646 program_async_controller(ADI_BOOT_DATA *bs)
650 /* Program the async banks controller. */
651 bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
652 bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
653 bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
657 /* Not all parts have these additional MMRs. */
659 bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
662 # ifdef CONFIG_EBIU_MODE_VAL
663 bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
665 # ifdef CONFIG_EBIU_FCTL_VAL
666 bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
673 BOOTROM_CALLED_FUNC_ATTR
674 void initcode(ADI_BOOT_DATA *bs)
676 ADI_BOOT_DATA bootstruct_scratch;
678 /* Setup NMI handler before anything else */
679 program_nmi_handler();
685 /* If the bootstruct is NULL, then it's because we're loading
686 * dynamically and not via LDR (bootrom). So set the struct to
687 * some scratch space.
690 bs = &bootstruct_scratch;
693 bool put_into_srfs = maybe_self_refresh(bs);
696 uint sdivB, divB, vcoB;
697 program_early_devices(bs, &sdivB, &divB, &vcoB);
700 u16 vr_ctl = program_clocks(bs, put_into_srfs);
703 update_serial_clocks(bs, sdivB, divB, vcoB);
706 program_memory_controller(bs, put_into_srfs);
709 check_hibernation(bs, vr_ctl, put_into_srfs);
712 program_async_controller(bs);
714 #ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
716 /* Tell the bootrom where our entry point is so that it knows
717 * where to jump to when finishing processing the LDR. This
718 * allows us to avoid small jump blocks in the LDR, and also
719 * works around anomaly 05000389 (init address in external
720 * memory causes bootrom to trigger external addressing IVHW).
722 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
723 bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE);