git.sur5r.net Git - u-boot/blob - arch/blackfin/cpu/initcode.c

   1 /*
   2  * initcode.c - Initialize the processor.  This is usually entails things
   3  * like external memory, voltage regulators, etc...  Note that this file
   4  * cannot make any function calls as it may be executed all by itself by
   5  * the Blackfin's bootrom in LDR format.
   6  *
   7  * Copyright (c) 2004-2011 Analog Devices Inc.
   8  *
   9  * Licensed under the GPL-2 or later.
  10  */
  11
  12 #define BFIN_IN_INITCODE
  13
  14 #include <config.h>
  15 #include <asm/blackfin.h>
  16 #include <asm/mach-common/bits/bootrom.h>
  17 #include <asm/mach-common/bits/core.h>
  18
  19 #define BUG() while (1) { asm volatile("emuexcpt;"); }
  20
  21 #include "serial.h"
  22
  23 #ifndef __ADSPBF60x__
  24 #include <asm/mach-common/bits/ebiu.h>
  25 #include <asm/mach-common/bits/pll.h>
  26 #else /* __ADSPBF60x__ */
  27 #include <asm/mach-common/bits/cgu.h>
  28
  29 #define CONFIG_BFIN_GET_DCLK_M \
  30         ((CONFIG_CLKIN_HZ*CONFIG_VCO_MULT)/(CONFIG_DCLK_DIV*1000000))
  31
  32 #ifndef CONFIG_DMC_DDRCFG
  33 #if ((CONFIG_BFIN_GET_DCLK_M != 125) && \
  34         (CONFIG_BFIN_GET_DCLK_M != 133) && \
  35         (CONFIG_BFIN_GET_DCLK_M != 150) && \
  36         (CONFIG_BFIN_GET_DCLK_M != 166) && \
  37         (CONFIG_BFIN_GET_DCLK_M != 200) && \
  38         (CONFIG_BFIN_GET_DCLK_M != 225) && \
  39         (CONFIG_BFIN_GET_DCLK_M != 250))
  40 #error "DDR2 CLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
  41 #endif
  42 #endif
  43
  44 /* DMC control bits */
  45 #define SRREQ                   0x8
  46
  47 /* DMC status bits */
  48 #define IDLE                    0x1
  49 #define MEMINITDONE             0x4
  50 #define SRACK                   0x8
  51 #define PDACK                   0x10
  52 #define DPDACK                  0x20
  53 #define DLLCALDONE              0x2000
  54 #define PENDREF                 0xF0000
  55 #define PHYRDPHASE              0xF00000
  56 #define PHYRDPHASE_OFFSET       20
  57
  58 /* DMC DLL control bits */
  59 #define DLLCALRDCNT             0xFF
  60 #define DATACYC_OFFSET          8
  61
  62 struct ddr_config {
  63         u32 ddr_clk;
  64         u32 dmc_ddrctl;
  65         u32 dmc_ddrcfg;
  66         u32 dmc_ddrtr0;
  67         u32 dmc_ddrtr1;
  68         u32 dmc_ddrtr2;
  69         u32 dmc_ddrmr;
  70         u32 dmc_ddrmr1;
  71 };
  72
  73 static struct ddr_config ddr_config_table[] = {
  74         [0] = {
  75                 .ddr_clk    = 125,      /* 125MHz */
  76                 .dmc_ddrctl = 0x00000904,
  77                 .dmc_ddrcfg = 0x00000422,
  78                 .dmc_ddrtr0 = 0x20705212,
  79                 .dmc_ddrtr1 = 0x201003CF,
  80                 .dmc_ddrtr2 = 0x00320107,
  81                 .dmc_ddrmr  = 0x00000422,
  82                 .dmc_ddrmr1 = 0x4,
  83         },
  84         [1] = {
  85                 .ddr_clk    = 133,      /* 133MHz */
  86                 .dmc_ddrctl = 0x00000904,
  87                 .dmc_ddrcfg = 0x00000422,
  88                 .dmc_ddrtr0 = 0x20806313,
  89                 .dmc_ddrtr1 = 0x2013040D,
  90                 .dmc_ddrtr2 = 0x00320108,
  91                 .dmc_ddrmr  = 0x00000632,
  92                 .dmc_ddrmr1 = 0x4,
  93         },
  94         [2] = {
  95                 .ddr_clk    = 150,      /* 150MHz */
  96                 .dmc_ddrctl = 0x00000904,
  97                 .dmc_ddrcfg = 0x00000422,
  98                 .dmc_ddrtr0 = 0x20A07323,
  99                 .dmc_ddrtr1 = 0x20160492,
 100                 .dmc_ddrtr2 = 0x00320209,
 101                 .dmc_ddrmr  = 0x00000632,
 102                 .dmc_ddrmr1 = 0x4,
 103         },
 104         [3] = {
 105                 .ddr_clk    = 166,      /* 166MHz */
 106                 .dmc_ddrctl = 0x00000904,
 107                 .dmc_ddrcfg = 0x00000422,
 108                 .dmc_ddrtr0 = 0x20A07323,
 109                 .dmc_ddrtr1 = 0x2016050E,
 110                 .dmc_ddrtr2 = 0x00320209,
 111                 .dmc_ddrmr  = 0x00000632,
 112                 .dmc_ddrmr1 = 0x4,
 113         },
 114         [4] = {
 115                 .ddr_clk    = 200,      /* 200MHz */
 116                 .dmc_ddrctl = 0x00000904,
 117                 .dmc_ddrcfg = 0x00000422,
 118                 .dmc_ddrtr0 = 0x20a07323,
 119                 .dmc_ddrtr1 = 0x2016050f,
 120                 .dmc_ddrtr2 = 0x00320509,
 121                 .dmc_ddrmr  = 0x00000632,
 122                 .dmc_ddrmr1 = 0x4,
 123         },
 124         [5] = {
 125                 .ddr_clk    = 225,      /* 225MHz */
 126                 .dmc_ddrctl = 0x00000904,
 127                 .dmc_ddrcfg = 0x00000422,
 128                 .dmc_ddrtr0 = 0x20E0A424,
 129                 .dmc_ddrtr1 = 0x302006DB,
 130                 .dmc_ddrtr2 = 0x0032020D,
 131                 .dmc_ddrmr  = 0x00000842,
 132                 .dmc_ddrmr1 = 0x4,
 133         },
 134         [6] = {
 135                 .ddr_clk    = 250,      /* 250MHz */
 136                 .dmc_ddrctl = 0x00000904,
 137                 .dmc_ddrcfg = 0x00000422,
 138                 .dmc_ddrtr0 = 0x20E0A424,
 139                 .dmc_ddrtr1 = 0x3020079E,
 140                 .dmc_ddrtr2 = 0x0032050D,
 141                 .dmc_ddrmr  = 0x00000842,
 142                 .dmc_ddrmr1 = 0x4,
 143         },
 144 };
 145 #endif /* __ADSPBF60x__ */
 146
 147 __attribute__((always_inline))
 148 static inline void serial_init(void)
 149 {
 150         uint32_t uart_base = UART_BASE;
 151
 152 #if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
 153 # ifdef BFIN_BOOT_UART_USE_RTS
 154 #  define BFIN_UART_USE_RTS 1
 155 # else
 156 #  define BFIN_UART_USE_RTS 0
 157 # endif
 158         if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
 159                 size_t i;
 160
 161                 /* force RTS rather than relying on auto RTS */
 162 #if BFIN_UART_HW_VER < 4
 163                 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL);
 164 #else
 165                 bfin_write32(&pUART->control, bfin_read32(&pUART->control) |
 166                                 FCPOL);
 167 #endif
 168
 169                 /* Wait for the line to clear up.  We cannot rely on UART
 170                  * registers as none of them reflect the status of the RSR.
 171                  * Instead, we'll sleep for ~10 bit times at 9600 baud.
 172                  * We can precalc things here by assuming boot values for
 173                  * PLL rather than loading registers and calculating.
 174                  *      baud    = SCLK / (16 ^ (1 - EDBO) * Divisor)
 175                  *      EDB0    = 0
 176                  *      Divisor = (SCLK / baud) / 16
 177                  *      SCLK    = baud * 16 * Divisor
 178                  *      SCLK    = (0x14 * CONFIG_CLKIN_HZ) / 5
 179                  *      CCLK    = (16 * Divisor * 5) * (9600 / 10)
 180                  * In reality, this will probably be just about 1 second delay,
 181                  * so assuming 9600 baud is OK (both as a very low and too high
 182                  * speed as this will buffer things enough).
 183                  */
 184 #define _NUMBITS (10)                                   /* how many bits to delay */
 185 #define _LOWBAUD (9600)                                 /* low baud rate */
 186 #define _SCLK    ((0x14 * CONFIG_CLKIN_HZ) / 5)         /* SCLK based on PLL */
 187 #define _DIVISOR ((_SCLK / _LOWBAUD) / 16)              /* UART DLL/DLH */
 188 #define _NUMINS  (3)                                    /* how many instructions in loop */
 189 #define _CCLK    (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS)
 190                 i = _CCLK;
 191                 while (i--)
 192                         asm volatile("" : : : "memory");
 193         }
 194 #endif
 195
 196         if (BFIN_DEBUG_EARLY_SERIAL) {
 197                 serial_early_init(uart_base);
 198                 serial_early_set_baud(uart_base, CONFIG_BAUDRATE);
 199         }
 200 }
 201
 202 __attribute__((always_inline))
 203 static inline void serial_deinit(void)
 204 {
 205 #if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
 206         uint32_t uart_base = UART_BASE;
 207
 208         if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
 209                 /* clear forced RTS rather than relying on auto RTS */
 210 #if BFIN_UART_HW_VER < 4
 211                 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL);
 212 #else
 213                 bfin_write32(&pUART->control, bfin_read32(&pUART->control) &
 214                                 ~FCPOL);
 215 #endif
 216         }
 217 #endif
 218 }
 219
 220 __attribute__((always_inline))
 221 static inline void serial_putc(char c)
 222 {
 223         uint32_t uart_base = UART_BASE;
 224
 225         if (!BFIN_DEBUG_EARLY_SERIAL)
 226                 return;
 227
 228         if (c == '\n')
 229                 serial_putc('\r');
 230
 231         bfin_write(&pUART->thr, c);
 232
 233         while (!(_lsr_read(pUART) & TEMT))
 234                 continue;
 235 }
 236
 237 #include "initcode.h"
 238
 239 __attribute__((always_inline)) static inline void
 240 program_nmi_handler(void)
 241 {
 242         u32 tmp1, tmp2;
 243
 244         /* Older bootroms don't create a dummy NMI handler,
 245          * so make one ourselves ASAP in case it fires.
 246          */
 247         if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS && !ANOMALY_05000219)
 248                 return;
 249
 250         asm volatile (
 251                 "%0 = RETS;" /* Save current RETS */
 252                 "CALL 1f;"   /* Figure out current PC */
 253                 "RTN;"       /* The simple NMI handler */
 254                 "1:"
 255                 "%1 = RETS;" /* Load addr of NMI handler */
 256                 "RETS = %0;" /* Restore RETS */
 257                 "[%2] = %1;" /* Write NMI handler */
 258                 : "=d"(tmp1), "=d"(tmp2)
 259                 : "ab"(EVT2)
 260         );
 261 }
 262
 263 /* Max SCLK can be 133MHz ... dividing that by (2*4) gives
 264  * us a freq of 16MHz for SPI which should generally be
 265  * slow enough for the slow reads the bootrom uses.
 266  */
 267 #if !defined(CONFIG_SPI_FLASH_SLOW_READ) && \
 268     ((defined(__ADSPBF52x__) && __SILICON_REVISION__ >= 2) || \
 269      (defined(__ADSPBF54x__) && __SILICON_REVISION__ >= 1))
 270 # define BOOTROM_SUPPORTS_SPI_FAST_READ 1
 271 #else
 272 # define BOOTROM_SUPPORTS_SPI_FAST_READ 0
 273 #endif
 274 #ifndef CONFIG_SPI_BAUD_INITBLOCK
 275 # define CONFIG_SPI_BAUD_INITBLOCK (BOOTROM_SUPPORTS_SPI_FAST_READ ? 2 : 4)
 276 #endif
 277 #ifdef SPI0_BAUD
 278 # define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD
 279 #endif
 280
 281 #ifdef __ADSPBF60x__
 282
 283 #ifndef CONFIG_CGU_CTL_VAL
 284 # define CONFIG_CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CONFIG_CLKIN_HALF)
 285 #endif
 286
 287 #ifndef CONFIG_CGU_DIV_VAL
 288 # define CONFIG_CGU_DIV_VAL \
 289         ((CONFIG_CCLK_DIV   << CSEL_P)   | \
 290          (CONFIG_SCLK0_DIV  << S0SEL_P)  | \
 291          (CONFIG_SCLK_DIV << SYSSEL_P) | \
 292          (CONFIG_SCLK1_DIV  << S1SEL_P)  | \
 293          (CONFIG_DCLK_DIV   << DSEL_P)   | \
 294          (CONFIG_OCLK_DIV   << OSEL_P))
 295 #endif
 296
 297 #else /* __ADSPBF60x__ */
 298
 299 /* PLL_DIV defines */
 300 #ifndef CONFIG_PLL_DIV_VAL
 301 # if (CONFIG_CCLK_DIV == 1)
 302 #  define CONFIG_CCLK_ACT_DIV CCLK_DIV1
 303 # elif (CONFIG_CCLK_DIV == 2)
 304 #  define CONFIG_CCLK_ACT_DIV CCLK_DIV2
 305 # elif (CONFIG_CCLK_DIV == 4)
 306 #  define CONFIG_CCLK_ACT_DIV CCLK_DIV4
 307 # elif (CONFIG_CCLK_DIV == 8)
 308 #  define CONFIG_CCLK_ACT_DIV CCLK_DIV8
 309 # else
 310 #  define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
 311 # endif
 312 # define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV)
 313 #endif
 314
 315 #ifndef CONFIG_PLL_LOCKCNT_VAL
 316 # define CONFIG_PLL_LOCKCNT_VAL 0x0300
 317 #endif
 318
 319 #ifndef CONFIG_PLL_CTL_VAL
 320 # define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF)
 321 #endif
 322
 323 /* Make sure our voltage value is sane so we don't blow up! */
 324 #ifndef CONFIG_VR_CTL_VAL
 325 # define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
 326 # if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__)
 327 #  define CCLK_VLEV_120 400000000
 328 #  define CCLK_VLEV_125 533000000
 329 # elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
 330 #  define CCLK_VLEV_120 401000000
 331 #  define CCLK_VLEV_125 401000000
 332 # elif defined(__ADSPBF561__)
 333 #  define CCLK_VLEV_120 300000000
 334 #  define CCLK_VLEV_125 501000000
 335 # endif
 336 # if BFIN_CCLK < CCLK_VLEV_120
 337 #  define CONFIG_VR_CTL_VLEV VLEV_120
 338 # elif BFIN_CCLK < CCLK_VLEV_125
 339 #  define CONFIG_VR_CTL_VLEV VLEV_125
 340 # else
 341 #  define CONFIG_VR_CTL_VLEV VLEV_130
 342 # endif
 343 # if defined(__ADSPBF52x__)     /* TBD; use default */
 344 #  undef CONFIG_VR_CTL_VLEV
 345 #  define CONFIG_VR_CTL_VLEV VLEV_110
 346 # elif defined(__ADSPBF54x__)   /* TBD; use default */
 347 #  undef CONFIG_VR_CTL_VLEV
 348 #  define CONFIG_VR_CTL_VLEV VLEV_120
 349 # elif defined(__ADSPBF538__) || defined(__ADSPBF539__) /* TBD; use default */
 350 #  undef CONFIG_VR_CTL_VLEV
 351 #  define CONFIG_VR_CTL_VLEV VLEV_125
 352 # endif
 353
 354 # ifdef CONFIG_BFIN_MAC
 355 #  define CONFIG_VR_CTL_CLKBUF CLKBUFOE
 356 # else
 357 #  define CONFIG_VR_CTL_CLKBUF 0
 358 # endif
 359
 360 # if defined(__ADSPBF52x__)
 361 #  define CONFIG_VR_CTL_FREQ FREQ_1000
 362 # else
 363 #  define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000)
 364 # endif
 365
 366 # define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
 367 #endif
 368
 369 /* some parts do not have an on-chip voltage regulator */
 370 #if defined(__ADSPBF51x__)
 371 # define CONFIG_HAS_VR 0
 372 # undef CONFIG_VR_CTL_VAL
 373 # define CONFIG_VR_CTL_VAL 0
 374 #else
 375 # define CONFIG_HAS_VR 1
 376 #endif
 377
 378 #if CONFIG_MEM_SIZE
 379 #ifndef EBIU_RSTCTL
 380 /* Blackfin with SDRAM */
 381 #ifndef CONFIG_EBIU_SDBCTL_VAL
 382 # if CONFIG_MEM_SIZE == 16
 383 #  define CONFIG_EBSZ_VAL EBSZ_16
 384 # elif CONFIG_MEM_SIZE == 32
 385 #  define CONFIG_EBSZ_VAL EBSZ_32
 386 # elif CONFIG_MEM_SIZE == 64
 387 #  define CONFIG_EBSZ_VAL EBSZ_64
 388 # elif CONFIG_MEM_SIZE == 128
 389 #  define CONFIG_EBSZ_VAL EBSZ_128
 390 # elif CONFIG_MEM_SIZE == 256
 391 #  define CONFIG_EBSZ_VAL EBSZ_256
 392 # elif CONFIG_MEM_SIZE == 512
 393 #  define CONFIG_EBSZ_VAL EBSZ_512
 394 # else
 395 #  error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_SIZE
 396 # endif
 397 # if CONFIG_MEM_ADD_WDTH == 8
 398 #  define CONFIG_EBCAW_VAL EBCAW_8
 399 # elif CONFIG_MEM_ADD_WDTH == 9
 400 #  define CONFIG_EBCAW_VAL EBCAW_9
 401 # elif CONFIG_MEM_ADD_WDTH == 10
 402 #  define CONFIG_EBCAW_VAL EBCAW_10
 403 # elif CONFIG_MEM_ADD_WDTH == 11
 404 #  define CONFIG_EBCAW_VAL EBCAW_11
 405 # else
 406 #  error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_ADD_WDTH
 407 # endif
 408 # define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE)
 409 #endif
 410 #endif
 411 #endif
 412
 413 /* Conflicting Column Address Widths Causes SDRAM Errors:
 414  * EB2CAW and EB3CAW must be the same
 415  */
 416 #if ANOMALY_05000362
 417 # if ((CONFIG_EBIU_SDBCTL_VAL & 0x30000000) >> 8) != (CONFIG_EBIU_SDBCTL_VAL & 0x00300000)
 418 #  error "Anomaly 05000362: EB2CAW and EB3CAW must be the same"
 419 # endif
 420 #endif
 421
 422 #endif /*  __ADSPBF60x__ */
 423
 424 __attribute__((always_inline)) static inline void
 425 program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
 426 {
 427         serial_putc('a');
 428
 429         /* Save the clock pieces that are used in baud rate calculation */
 430         if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
 431                 serial_putc('b');
 432 #ifdef __ADSPBF60x__
 433                 *sdivB = bfin_read_CGU_DIV();
 434                 *sdivB = ((*sdivB >> 8) & 0x1f) * ((*sdivB >> 5) & 0x7);
 435                 *vcoB = (bfin_read_CGU_CTL() >> 8) & 0x7f;
 436 #else
 437                 *sdivB = bfin_read_PLL_DIV() & 0xf;
 438                 *vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
 439 #endif
 440                 *divB = serial_early_get_div();
 441                 serial_putc('c');
 442         }
 443
 444         serial_putc('d');
 445
 446 #ifdef CONFIG_HW_WATCHDOG
 447 # ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
 448 #  define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
 449 # endif
 450         /* Program the watchdog with an initial timeout of ~20 seconds.
 451          * Hopefully that should be long enough to load the u-boot LDR
 452          * (from wherever) and then the common u-boot code can take over.
 453          * In bypass mode, the start.S would have already set a much lower
 454          * timeout, so don't clobber that.
 455          */
 456         if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
 457                 serial_putc('e');
 458 #ifdef __ADSPBF60x__
 459                 bfin_write_SEC_GCTL(0x2);
 460                 SSYNC();
 461                 bfin_write_SEC_FCTL(0xc1);
 462                 bfin_write_SEC_SCTL(2, bfin_read_SEC_SCTL(2) | 0x6);
 463
 464                 bfin_write_SEC_CCTL(0x2);
 465                 SSYNC();
 466                 bfin_write_SEC_GCTL(0x1);
 467                 bfin_write_SEC_CCTL(0x1);
 468 #endif
 469                 bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
 470 #if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART
 471                 bfin_write_WDOG_CTL(0);
 472 #endif
 473                 serial_putc('f');
 474         }
 475 #endif
 476
 477         serial_putc('g');
 478
 479         /* Blackfin bootroms use the SPI slow read opcode instead of the SPI
 480          * fast read, so we need to slow down the SPI clock a lot more during
 481          * boot.  Once we switch over to u-boot's SPI flash driver, we'll
 482          * increase the speed appropriately.
 483          */
 484 #ifdef SPI_BAUD
 485         if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
 486                 serial_putc('h');
 487                 if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4)
 488                         bs->dFlags |= BFLAG_FASTREAD;
 489                 bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
 490                 serial_putc('i');
 491         }
 492 #endif
 493
 494         serial_putc('j');
 495 }
 496
 497 __attribute__((always_inline)) static inline bool
 498 maybe_self_refresh(ADI_BOOT_DATA *bs)
 499 {
 500         serial_putc('a');
 501
 502         if (!CONFIG_MEM_SIZE)
 503                 return false;
 504
 505 #ifdef __ADSPBF60x__
 506         /* resume from hibernate, return false let ddr initialize */
 507         if ((bfin_read32(DPM0_STAT) & 0xF0) == 0x50) {
 508                 serial_putc('b');
 509                 return false;
 510         }
 511
 512 #else /* __ADSPBF60x__ */
 513
 514         /* If external memory is enabled, put it into self refresh first. */
 515 #if defined(EBIU_RSTCTL)
 516         if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
 517                 serial_putc('b');
 518                 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ);
 519                 return true;
 520         }
 521 #elif defined(EBIU_SDGCTL)
 522         if (bfin_read_EBIU_SDBCTL() & EBE) {
 523                 serial_putc('b');
 524                 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
 525                 return true;
 526         }
 527 #endif
 528
 529 #endif /* __ADSPBF60x__ */
 530         serial_putc('c');
 531
 532         return false;
 533 }
 534
 535 __attribute__((always_inline)) static inline u16
 536 program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
 537 {
 538         u16 vr_ctl;
 539
 540         serial_putc('a');
 541
 542 #ifdef __ADSPBF60x__
 543         if (bfin_read_DMC0_STAT() & MEMINITDONE) {
 544                 bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ);
 545                 SSYNC();
 546                 while (!(bfin_read_DMC0_STAT() & SRACK))
 547                         continue;
 548         }
 549
 550         /* Don't set the same value of MSEL and DF to CGU_CTL */
 551         if ((bfin_read_CGU_CTL() & (MSEL_MASK | DF_MASK))
 552                         != CONFIG_CGU_CTL_VAL) {
 553                 bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL);
 554                 bfin_write_CGU_CTL(CONFIG_CGU_CTL_VAL);
 555                 while ((bfin_read_CGU_STAT() & (CLKSALGN | PLLBP)) ||
 556                                 !(bfin_read_CGU_STAT() & PLLLK))
 557                         continue;
 558         }
 559
 560         bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL | UPDT);
 561         while (bfin_read_CGU_STAT() & CLKSALGN)
 562                 continue;
 563
 564         if (bfin_read_DMC0_STAT() & MEMINITDONE) {
 565                 bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ);
 566                 SSYNC();
 567                 while (bfin_read_DMC0_STAT() & SRACK)
 568                         continue;
 569         }
 570
 571 #else /* __ADSPBF60x__ */
 572
 573         vr_ctl = bfin_read_VR_CTL();
 574
 575         serial_putc('b');
 576
 577         /* If we're entering self refresh, make sure it has happened. */
 578         if (put_into_srfs)
 579 #if defined(EBIU_RSTCTL)
 580                 while (!(bfin_read_EBIU_RSTCTL() & SRACK))
 581                         continue;
 582 #elif defined(EBIU_SDGCTL)
 583                 while (!(bfin_read_EBIU_SDSTAT() & SDSRA))
 584                         continue;
 585 #else
 586                 ;
 587 #endif
 588
 589         serial_putc('c');
 590
 591         /* With newer bootroms, we use the helper function to set up
 592          * the memory controller.  Older bootroms lacks such helpers
 593          * so we do it ourselves.
 594          */
 595         if (!ANOMALY_05000386) {
 596                 serial_putc('d');
 597
 598                 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
 599                 ADI_SYSCTRL_VALUES memory_settings;
 600                 uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_LOCKCNT;
 601                 if (!ANOMALY_05000440)
 602                         actions |= SYSCTRL_PLLDIV;
 603                 if (CONFIG_HAS_VR) {
 604                         actions |= SYSCTRL_VRCTL;
 605                         if (CONFIG_VR_CTL_VAL & FREQ_MASK)
 606                                 actions |= SYSCTRL_INTVOLTAGE;
 607                         else
 608                                 actions |= SYSCTRL_EXTVOLTAGE;
 609                         memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
 610                 } else
 611                         actions |= SYSCTRL_EXTVOLTAGE;
 612                 memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
 613                 memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
 614                 memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
 615 #if ANOMALY_05000432
 616                 bfin_write_SIC_IWR1(0);
 617 #endif
 618                 serial_putc('e');
 619                 bfrom_SysControl(actions, &memory_settings, NULL);
 620                 serial_putc('f');
 621                 if (ANOMALY_05000440)
 622                         bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
 623 #if ANOMALY_05000432
 624                 bfin_write_SIC_IWR1(-1);
 625 #endif
 626 #if ANOMALY_05000171
 627                 bfin_write_SICA_IWR0(-1);
 628                 bfin_write_SICA_IWR1(-1);
 629 #endif
 630                 serial_putc('g');
 631         } else {
 632                 serial_putc('h');
 633
 634                 /* Disable all peripheral wakeups except for the PLL event. */
 635 #ifdef SIC_IWR0
 636                 bfin_write_SIC_IWR0(1);
 637                 bfin_write_SIC_IWR1(0);
 638 # ifdef SIC_IWR2
 639                 bfin_write_SIC_IWR2(0);
 640 # endif
 641 #elif defined(SICA_IWR0)
 642                 bfin_write_SICA_IWR0(1);
 643                 bfin_write_SICA_IWR1(0);
 644 #elif defined(SIC_IWR)
 645                 bfin_write_SIC_IWR(1);
 646 #endif
 647
 648                 serial_putc('i');
 649
 650                 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
 651                 bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
 652
 653                 serial_putc('j');
 654
 655                 /* Only reprogram when needed to avoid triggering unnecessary
 656                  * PLL relock sequences.
 657                  */
 658                 if (vr_ctl != CONFIG_VR_CTL_VAL) {
 659                         serial_putc('?');
 660                         bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
 661                         asm("idle;");
 662                         serial_putc('!');
 663                 }
 664
 665                 serial_putc('k');
 666
 667                 bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
 668
 669                 serial_putc('l');
 670
 671                 /* Only reprogram when needed to avoid triggering unnecessary
 672                  * PLL relock sequences.
 673                  */
 674                 if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
 675                         serial_putc('?');
 676                         bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
 677                         asm("idle;");
 678                         serial_putc('!');
 679                 }
 680
 681                 serial_putc('m');
 682
 683                 /* Restore all peripheral wakeups. */
 684 #ifdef SIC_IWR0
 685                 bfin_write_SIC_IWR0(-1);
 686                 bfin_write_SIC_IWR1(-1);
 687 # ifdef SIC_IWR2
 688                 bfin_write_SIC_IWR2(-1);
 689 # endif
 690 #elif defined(SICA_IWR0)
 691                 bfin_write_SICA_IWR0(-1);
 692                 bfin_write_SICA_IWR1(-1);
 693 #elif defined(SIC_IWR)
 694                 bfin_write_SIC_IWR(-1);
 695 #endif
 696
 697                 serial_putc('n');
 698         }
 699
 700 #endif /* __ADSPBF60x__ */
 701
 702         serial_putc('o');
 703
 704         return vr_ctl;
 705 }
 706
 707 __attribute__((always_inline)) static inline void
 708 update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
 709 {
 710         /* Since we've changed the SCLK above, we may need to update
 711          * the UART divisors (UART baud rates are based on SCLK).
 712          * Do the division by hand as there are no native instructions
 713          * for dividing which means we'd generate a libgcc reference.
 714          */
 715         unsigned int sdivR, vcoR;
 716         unsigned int dividend = sdivB * divB * vcoR;
 717         unsigned int divisor = vcoB * sdivR;
 718         unsigned int quotient;
 719
 720         serial_putc('a');
 721
 722 #ifdef __ADSPBF60x__
 723         sdivR = bfin_read_CGU_DIV();
 724         sdivR = ((sdivR >> 8) & 0x1f) * ((sdivR >> 5) & 0x7);
 725         vcoR = (bfin_read_CGU_CTL() >> 8) & 0x7f;
 726 #else
 727         sdivR = bfin_read_PLL_DIV() & 0xf;
 728         vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
 729 #endif
 730         quotient = early_division(dividend, divisor);
 731         serial_early_put_div(quotient - ANOMALY_05000230);
 732         serial_putc('c');
 733 }
 734
 735 __attribute__((always_inline)) static inline void
 736 program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
 737 {
 738         serial_putc('a');
 739
 740         if (!CONFIG_MEM_SIZE)
 741                 return;
 742
 743         serial_putc('b');
 744
 745 #ifdef __ADSPBF60x__
 746         int dlldatacycle;
 747         int dll_ctl;
 748         int i = 0;
 749
 750         if (CONFIG_BFIN_GET_DCLK_M ==  125)
 751                 i = 0;
 752         else if (CONFIG_BFIN_GET_DCLK_M ==  133)
 753                 i = 1;
 754         else if (CONFIG_BFIN_GET_DCLK_M ==  150)
 755                 i = 2;
 756         else if (CONFIG_BFIN_GET_DCLK_M ==  166)
 757                 i = 3;
 758         else if (CONFIG_BFIN_GET_DCLK_M ==  200)
 759                 i = 4;
 760         else if (CONFIG_BFIN_GET_DCLK_M ==  225)
 761                 i = 5;
 762         else if (CONFIG_BFIN_GET_DCLK_M ==  250)
 763                 i = 6;
 764
 765 #if 0
 766         for (i = 0; i < ARRAY_SIZE(ddr_config_table); i++)
 767                 if (CONFIG_BFIN_GET_DCLK_M == ddr_config_table[i].ddr_clk)
 768                         break;
 769 #endif
 770
 771 #ifndef CONFIG_DMC_DDRCFG
 772         bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg);
 773 #else
 774         bfin_write_DMC0_CFG(CONFIG_DMC_DDRCFG);
 775 #endif
 776 #ifndef CONFIG_DMC_DDRTR0
 777         bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0);
 778 #else
 779         bfin_write_DMC0_TR0(CONFIG_DMC_DDRTR0);
 780 #endif
 781 #ifndef CONFIG_DMC_DDRTR1
 782         bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1);
 783 #else
 784         bfin_write_DMC0_TR1(CONFIG_DMC_DDRTR1);
 785 #endif
 786 #ifndef CONFIG_DMC_DDRTR2
 787         bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2);
 788 #else
 789         bfin_write_DMC0_TR2(CONFIG_DMC_DDRTR2);
 790 #endif
 791 #ifndef CONFIG_DMC_DDRMR
 792         bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr);
 793 #else
 794         bfin_write_DMC0_MR(CONFIG_DMC_DDRMR);
 795 #endif
 796 #ifndef CONFIG_DMC_DDREMR1
 797         bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1);
 798 #else
 799         bfin_write_DMC0_EMR1(CONFIG_DMC_DDREMR1);
 800 #endif
 801 #ifndef CONFIG_DMC_DDRCTL
 802         bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl);
 803 #else
 804         bfin_write_DMC0_CTL(CONFIG_DMC_DDRCTL);
 805 #endif
 806
 807         SSYNC();
 808         while (!(bfin_read_DMC0_STAT() & MEMINITDONE))
 809                 continue;
 810
 811         dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >>
 812                         PHYRDPHASE_OFFSET;
 813         dll_ctl = bfin_read_DMC0_DLLCTL();
 814         dll_ctl &= 0x0ff;
 815         bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET));
 816
 817         SSYNC();
 818         while (!(bfin_read_DMC0_STAT() & DLLCALDONE))
 819                 continue;
 820         serial_putc('!');
 821
 822 #else /* __ADSPBF60x__ */
 823
 824         /* Program the external memory controller before we come out of
 825          * self-refresh.  This only works with our SDRAM controller.
 826          */
 827 #ifdef EBIU_SDGCTL
 828 # ifdef CONFIG_EBIU_SDRRC_VAL
 829         bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
 830 # endif
 831 # ifdef CONFIG_EBIU_SDBCTL_VAL
 832         bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
 833 # endif
 834 # ifdef CONFIG_EBIU_SDGCTL_VAL
 835         bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
 836 # endif
 837 #endif
 838
 839         serial_putc('c');
 840
 841         /* Now that we've reprogrammed, take things out of self refresh. */
 842         if (put_into_srfs)
 843 #if defined(EBIU_RSTCTL)
 844                 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
 845 #elif defined(EBIU_SDGCTL)
 846                 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS));
 847 #endif
 848
 849         serial_putc('d');
 850
 851         /* Our DDR controller sucks and cannot be programmed while in
 852          * self-refresh.  So we have to pull it out before programming.
 853          */
 854 #ifdef EBIU_RSTCTL
 855 # ifdef CONFIG_EBIU_RSTCTL_VAL
 856         bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
 857 # endif
 858 # ifdef CONFIG_EBIU_DDRCTL0_VAL
 859         bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
 860 # endif
 861 # ifdef CONFIG_EBIU_DDRCTL1_VAL
 862         bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
 863 # endif
 864 # ifdef CONFIG_EBIU_DDRCTL2_VAL
 865         bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
 866 # endif
 867 # ifdef CONFIG_EBIU_DDRCTL3_VAL
 868         /* default is disable, so don't need to force this */
 869         bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
 870 # endif
 871 # ifdef CONFIG_EBIU_DDRQUE_VAL
 872         bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | CONFIG_EBIU_DDRQUE_VAL);
 873 # endif
 874 #endif
 875
 876 #endif /* __ADSPBF60x__ */
 877         serial_putc('e');
 878 }
 879
 880 __attribute__((always_inline)) static inline void
 881 check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs)
 882 {
 883         serial_putc('a');
 884
 885         if (!CONFIG_MEM_SIZE)
 886                 return;
 887
 888         serial_putc('b');
 889 #ifdef __ADSPBF60x__
 890         if (bfin_read32(DPM0_RESTORE0) != 0) {
 891                 uint32_t reg = bfin_read_DMC0_CTL();
 892                 reg &= ~0x8;
 893                 bfin_write_DMC0_CTL(reg);
 894
 895                 while ((bfin_read_DMC0_STAT() & 0x8))
 896                         continue;
 897                 while (!(bfin_read_DMC0_STAT() & 0x1))
 898                         continue;
 899
 900                 serial_putc('z');
 901                 uint32_t *hibernate_magic = bfin_read32(DPM0_RESTORE4);
 902                 SSYNC(); /* make sure memory controller is done */
 903                 if (hibernate_magic[0] == 0xDEADBEEF) {
 904                         serial_putc('c');
 905                         SSYNC();
 906                         bfin_write_EVT15(hibernate_magic[1]);
 907                         bfin_write_IMASK(EVT_IVG15);
 908                         __asm__ __volatile__ (
 909                                 /* load reti early to avoid anomaly 281 */
 910                                 "reti = %2;"
 911                                 /* clear hibernate magic */
 912                                 "[%0] = %1;"
 913                                 /* load stack pointer */
 914                                 "SP = [%0 + 8];"
 915                                 /* lower ourselves from reset ivg to ivg15 */
 916                                 "raise 15;"
 917                                 "nop;nop;nop;"
 918                                 "rti;"
 919                                 :
 920                                 : "p"(hibernate_magic),
 921                                 "d"(0x2000 /* jump.s 0 */),
 922                                 "d"(0xffa00000)
 923                         );
 924                 }
 925
 926
 927         }
 928 #else
 929         /* Are we coming out of hibernate (suspend to memory) ?
 930          * The memory layout is:
 931          * 0x0: hibernate magic for anomaly 307 (0xDEADBEEF)
 932          * 0x4: return address
 933          * 0x8: stack pointer
 934          *
 935          * SCKELOW is unreliable on older parts (anomaly 307)
 936          */
 937         if (ANOMALY_05000307 || vr_ctl & 0x8000) {
 938                 uint32_t *hibernate_magic = 0;
 939
 940                 SSYNC();
 941                 if (hibernate_magic[0] == 0xDEADBEEF) {
 942                         serial_putc('c');
 943                         bfin_write_EVT15(hibernate_magic[1]);
 944                         bfin_write_IMASK(EVT_IVG15);
 945                         __asm__ __volatile__ (
 946                                 /* load reti early to avoid anomaly 281 */
 947                                 "reti = %0;"
 948                                 /* clear hibernate magic */
 949                                 "[%0] = %1;"
 950                                 /* load stack pointer */
 951                                 "SP = [%0 + 8];"
 952                                 /* lower ourselves from reset ivg to ivg15 */
 953                                 "raise 15;"
 954                                 "rti;"
 955                                 :
 956                                 : "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */)
 957                         );
 958                 }
 959                 serial_putc('d');
 960         }
 961 #endif
 962
 963         serial_putc('e');
 964 }
 965
 966 BOOTROM_CALLED_FUNC_ATTR
 967 void initcode(ADI_BOOT_DATA *bs)
 968 {
 969         ADI_BOOT_DATA bootstruct_scratch;
 970
 971         /* Setup NMI handler before anything else */
 972         program_nmi_handler();
 973
 974         serial_init();
 975
 976         serial_putc('A');
 977
 978         /* If the bootstruct is NULL, then it's because we're loading
 979          * dynamically and not via LDR (bootrom).  So set the struct to
 980          * some scratch space.
 981          */
 982         if (!bs)
 983                 bs = &bootstruct_scratch;
 984
 985         serial_putc('B');
 986         bool put_into_srfs = maybe_self_refresh(bs);
 987
 988         serial_putc('C');
 989         uint sdivB, divB, vcoB;
 990         program_early_devices(bs, &sdivB, &divB, &vcoB);
 991
 992         serial_putc('D');
 993         u16 vr_ctl = program_clocks(bs, put_into_srfs);
 994
 995         serial_putc('E');
 996         update_serial_clocks(bs, sdivB, divB, vcoB);
 997
 998         serial_putc('F');
 999         program_memory_controller(bs, put_into_srfs);
1000
1001         serial_putc('G');
1002         check_hibernation(bs, vr_ctl, put_into_srfs);
1003
1004         serial_putc('H');
1005         program_async_controller(bs);
1006
1007 #ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
1008         serial_putc('I');
1009         /* Tell the bootrom where our entry point is so that it knows
1010          * where to jump to when finishing processing the LDR.  This
1011          * allows us to avoid small jump blocks in the LDR, and also
1012          * works around anomaly 05000389 (init address in external
1013          * memory causes bootrom to trigger external addressing IVHW).
1014          */
1015         if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
1016                 bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE);
1017 #endif
1018
1019         serial_putc('>');
1020         serial_putc('\n');
1021
1022         serial_deinit();
1023 }