2 * initcode.c - Initialize the processor. This is usually entails things
3 * like external memory, voltage regulators, etc... Note that this file
4 * cannot make any function calls as it may be executed all by itself by
5 * the Blackfin's bootrom in LDR format.
7 * Copyright (c) 2004-2008 Analog Devices Inc.
9 * Licensed under the GPL-2 or later.
12 #define BFIN_IN_INITCODE
15 #include <asm/blackfin.h>
16 #include <asm/mach-common/bits/bootrom.h>
17 #include <asm/mach-common/bits/core.h>
18 #include <asm/mach-common/bits/ebiu.h>
19 #include <asm/mach-common/bits/pll.h>
20 #include <asm/mach-common/bits/uart.h>
24 __attribute__((always_inline))
25 static inline void serial_init(void)
28 # ifdef BFIN_BOOT_UART_USE_RTS
29 # define BFIN_UART_USE_RTS 1
31 # define BFIN_UART_USE_RTS 0
33 if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
36 /* force RTS rather than relying on auto RTS */
37 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL);
39 /* Wait for the line to clear up. We cannot rely on UART
40 * registers as none of them reflect the status of the RSR.
41 * Instead, we'll sleep for ~10 bit times at 9600 baud.
42 * We can precalc things here by assuming boot values for
43 * PLL rather than loading registers and calculating.
44 * baud = SCLK / (16 ^ (1 - EDBO) * Divisor)
46 * Divisor = (SCLK / baud) / 16
47 * SCLK = baud * 16 * Divisor
48 * SCLK = (0x14 * CONFIG_CLKIN_HZ) / 5
49 * CCLK = (16 * Divisor * 5) * (9600 / 10)
50 * In reality, this will probably be just about 1 second delay,
51 * so assuming 9600 baud is OK (both as a very low and too high
52 * speed as this will buffer things enough).
54 #define _NUMBITS (10) /* how many bits to delay */
55 #define _LOWBAUD (9600) /* low baud rate */
56 #define _SCLK ((0x14 * CONFIG_CLKIN_HZ) / 5) /* SCLK based on PLL */
57 #define _DIVISOR ((_SCLK / _LOWBAUD) / 16) /* UART DLL/DLH */
58 #define _NUMINS (3) /* how many instructions in loop */
59 #define _CCLK (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS)
62 asm volatile("" : : : "memory");
66 if (BFIN_DEBUG_EARLY_SERIAL) {
67 int ucen = bfin_read16(&pUART->gctl) & UCEN;
70 /* If the UART is off, that means we need to program
71 * the baud rate ourselves initially.
74 serial_early_set_baud(CONFIG_BAUDRATE);
78 __attribute__((always_inline))
79 static inline void serial_deinit(void)
82 if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
83 /* clear forced RTS rather than relying on auto RTS */
84 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL);
89 __attribute__((always_inline))
90 static inline void serial_putc(char c)
92 if (!BFIN_DEBUG_EARLY_SERIAL)
98 bfin_write16(&pUART->thr, c);
100 while (!(bfin_read16(&pUART->lsr) & TEMT))
104 __attribute__((always_inline)) static inline void
105 program_nmi_handler(void)
109 /* Older bootroms don't create a dummy NMI handler,
110 * so make one ourselves ASAP in case it fires.
112 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS && !ANOMALY_05000219)
116 "%0 = RETS;" /* Save current RETS */
117 "CALL 1f;" /* Figure out current PC */
118 "RTN;" /* The simple NMI handler */
120 "%1 = RETS;" /* Load addr of NMI handler */
121 "RETS = %0;" /* Restore RETS */
122 "[%2] = %1;" /* Write NMI handler */
123 : "=r"(tmp1), "=r"(tmp2) : "ab"(EVT2)
127 /* Max SCLK can be 133MHz ... dividing that by (2*4) gives
128 * us a freq of 16MHz for SPI which should generally be
129 * slow enough for the slow reads the bootrom uses.
131 #if !defined(CONFIG_SPI_FLASH_SLOW_READ) && \
132 ((defined(__ADSPBF52x__) && __SILICON_REVISION__ >= 2) || \
133 (defined(__ADSPBF54x__) && __SILICON_REVISION__ >= 1))
134 # define BOOTROM_SUPPORTS_SPI_FAST_READ 1
136 # define BOOTROM_SUPPORTS_SPI_FAST_READ 0
138 #ifndef CONFIG_SPI_BAUD_INITBLOCK
139 # define CONFIG_SPI_BAUD_INITBLOCK (BOOTROM_SUPPORTS_SPI_FAST_READ ? 2 : 4)
142 # define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD
145 /* PLL_DIV defines */
146 #ifndef CONFIG_PLL_DIV_VAL
147 # if (CONFIG_CCLK_DIV == 1)
148 # define CONFIG_CCLK_ACT_DIV CCLK_DIV1
149 # elif (CONFIG_CCLK_DIV == 2)
150 # define CONFIG_CCLK_ACT_DIV CCLK_DIV2
151 # elif (CONFIG_CCLK_DIV == 4)
152 # define CONFIG_CCLK_ACT_DIV CCLK_DIV4
153 # elif (CONFIG_CCLK_DIV == 8)
154 # define CONFIG_CCLK_ACT_DIV CCLK_DIV8
156 # define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
158 # define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV)
161 #ifndef CONFIG_PLL_LOCKCNT_VAL
162 # define CONFIG_PLL_LOCKCNT_VAL 0x0300
165 #ifndef CONFIG_PLL_CTL_VAL
166 # define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF)
169 #ifndef CONFIG_EBIU_RSTCTL_VAL
170 # define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
172 #if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0)
173 # error invalid EBIU_RSTCTL value: must not set reserved bits
176 #ifndef CONFIG_EBIU_MBSCTL_VAL
177 # define CONFIG_EBIU_MBSCTL_VAL 0
180 #if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0)
181 # error invalid EBIU_DDRQUE value: must not set reserved bits
184 /* Make sure our voltage value is sane so we don't blow up! */
185 #ifndef CONFIG_VR_CTL_VAL
186 # define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
187 # if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__)
188 # define CCLK_VLEV_120 400000000
189 # define CCLK_VLEV_125 533000000
190 # elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
191 # define CCLK_VLEV_120 401000000
192 # define CCLK_VLEV_125 401000000
193 # elif defined(__ADSPBF561__)
194 # define CCLK_VLEV_120 300000000
195 # define CCLK_VLEV_125 501000000
197 # if BFIN_CCLK < CCLK_VLEV_120
198 # define CONFIG_VR_CTL_VLEV VLEV_120
199 # elif BFIN_CCLK < CCLK_VLEV_125
200 # define CONFIG_VR_CTL_VLEV VLEV_125
202 # define CONFIG_VR_CTL_VLEV VLEV_130
204 # if defined(__ADSPBF52x__) /* TBD; use default */
205 # undef CONFIG_VR_CTL_VLEV
206 # define CONFIG_VR_CTL_VLEV VLEV_110
207 # elif defined(__ADSPBF54x__) /* TBD; use default */
208 # undef CONFIG_VR_CTL_VLEV
209 # define CONFIG_VR_CTL_VLEV VLEV_120
210 # elif defined(__ADSPBF538__) || defined(__ADSPBF539__) /* TBD; use default */
211 # undef CONFIG_VR_CTL_VLEV
212 # define CONFIG_VR_CTL_VLEV VLEV_125
215 # ifdef CONFIG_BFIN_MAC
216 # define CONFIG_VR_CTL_CLKBUF CLKBUFOE
218 # define CONFIG_VR_CTL_CLKBUF 0
221 # if defined(__ADSPBF52x__)
222 # define CONFIG_VR_CTL_FREQ FREQ_1000
224 # define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000)
227 # define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
230 /* some parts do not have an on-chip voltage regulator */
231 #if defined(__ADSPBF51x__)
232 # define CONFIG_HAS_VR 0
233 # undef CONFIG_VR_CTL_VAL
234 # define CONFIG_VR_CTL_VAL 0
236 # define CONFIG_HAS_VR 1
241 /* Blackfin with SDRAM */
242 #ifndef CONFIG_EBIU_SDBCTL_VAL
243 # if CONFIG_MEM_SIZE == 16
244 # define CONFIG_EBSZ_VAL EBSZ_16
245 # elif CONFIG_MEM_SIZE == 32
246 # define CONFIG_EBSZ_VAL EBSZ_32
247 # elif CONFIG_MEM_SIZE == 64
248 # define CONFIG_EBSZ_VAL EBSZ_64
249 # elif CONFIG_MEM_SIZE == 128
250 # define CONFIG_EBSZ_VAL EBSZ_128
251 # elif CONFIG_MEM_SIZE == 256
252 # define CONFIG_EBSZ_VAL EBSZ_256
253 # elif CONFIG_MEM_SIZE == 512
254 # define CONFIG_EBSZ_VAL EBSZ_512
256 # error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_SIZE
258 # if CONFIG_MEM_ADD_WDTH == 8
259 # define CONFIG_EBCAW_VAL EBCAW_8
260 # elif CONFIG_MEM_ADD_WDTH == 9
261 # define CONFIG_EBCAW_VAL EBCAW_9
262 # elif CONFIG_MEM_ADD_WDTH == 10
263 # define CONFIG_EBCAW_VAL EBCAW_10
264 # elif CONFIG_MEM_ADD_WDTH == 11
265 # define CONFIG_EBCAW_VAL EBCAW_11
267 # error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_ADD_WDTH
269 # define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE)
274 /* Conflicting Column Address Widths Causes SDRAM Errors:
275 * EB2CAW and EB3CAW must be the same
278 # if ((CONFIG_EBIU_SDBCTL_VAL & 0x30000000) >> 8) != (CONFIG_EBIU_SDBCTL_VAL & 0x00300000)
279 # error "Anomaly 05000362: EB2CAW and EB3CAW must be the same"
283 __attribute__((always_inline)) static inline void
284 program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
288 /* Save the clock pieces that are used in baud rate calculation */
289 if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
291 *sdivB = bfin_read_PLL_DIV() & 0xf;
292 *vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
293 *divB = serial_early_get_div();
299 #ifdef CONFIG_HW_WATCHDOG
300 # ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
301 # define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
303 /* Program the watchdog with an initial timeout of ~20 seconds.
304 * Hopefully that should be long enough to load the u-boot LDR
305 * (from wherever) and then the common u-boot code can take over.
306 * In bypass mode, the start.S would have already set a much lower
307 * timeout, so don't clobber that.
309 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
311 bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
312 bfin_write_WDOG_CTL(0);
319 /* Blackfin bootroms use the SPI slow read opcode instead of the SPI
320 * fast read, so we need to slow down the SPI clock a lot more during
321 * boot. Once we switch over to u-boot's SPI flash driver, we'll
322 * increase the speed appropriately.
324 if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
326 if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4)
327 bs->dFlags |= BFLAG_FASTREAD;
328 bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
335 __attribute__((always_inline)) static inline bool
336 maybe_self_refresh(ADI_BOOT_DATA *bs)
340 if (!CONFIG_MEM_SIZE)
343 /* If external memory is enabled, put it into self refresh first. */
344 #if defined(EBIU_RSTCTL)
345 if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
347 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ);
350 #elif defined(EBIU_SDGCTL)
351 if (bfin_read_EBIU_SDBCTL() & EBE) {
353 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
363 __attribute__((always_inline)) static inline u16
364 program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
370 vr_ctl = bfin_read_VR_CTL();
374 /* If we're entering self refresh, make sure it has happened. */
376 #if defined(EBIU_RSTCTL)
377 while (!(bfin_read_EBIU_RSTCTL() & SRACK))
379 #elif defined(EBIU_SDGCTL)
380 while (!(bfin_read_EBIU_SDSTAT() & SDSRA))
388 /* With newer bootroms, we use the helper function to set up
389 * the memory controller. Older bootroms lacks such helpers
390 * so we do it ourselves.
392 if (!ANOMALY_05000386) {
395 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
396 ADI_SYSCTRL_VALUES memory_settings;
397 uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_LOCKCNT;
398 if (!ANOMALY_05000440)
399 actions |= SYSCTRL_PLLDIV;
401 actions |= SYSCTRL_VRCTL;
402 if (CONFIG_VR_CTL_VAL & FREQ_MASK)
403 actions |= SYSCTRL_INTVOLTAGE;
405 actions |= SYSCTRL_EXTVOLTAGE;
406 memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
408 actions |= SYSCTRL_EXTVOLTAGE;
409 memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
410 memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
411 memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
413 bfin_write_SIC_IWR1(0);
416 bfrom_SysControl(actions, &memory_settings, NULL);
418 if (ANOMALY_05000440)
419 bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
421 bfin_write_SIC_IWR1(-1);
424 bfin_write_SICA_IWR0(-1);
425 bfin_write_SICA_IWR1(-1);
431 /* Disable all peripheral wakeups except for the PLL event. */
433 bfin_write_SIC_IWR0(1);
434 bfin_write_SIC_IWR1(0);
436 bfin_write_SIC_IWR2(0);
438 #elif defined(SICA_IWR0)
439 bfin_write_SICA_IWR0(1);
440 bfin_write_SICA_IWR1(0);
442 bfin_write_SIC_IWR(1);
447 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
448 bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
452 /* Only reprogram when needed to avoid triggering unnecessary
453 * PLL relock sequences.
455 if (vr_ctl != CONFIG_VR_CTL_VAL) {
457 bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
464 bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
468 /* Only reprogram when needed to avoid triggering unnecessary
469 * PLL relock sequences.
471 if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
473 bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
480 /* Restore all peripheral wakeups. */
482 bfin_write_SIC_IWR0(-1);
483 bfin_write_SIC_IWR1(-1);
485 bfin_write_SIC_IWR2(-1);
487 #elif defined(SICA_IWR0)
488 bfin_write_SICA_IWR0(-1);
489 bfin_write_SICA_IWR1(-1);
491 bfin_write_SIC_IWR(-1);
502 __attribute__((always_inline)) static inline void
503 update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
507 /* Since we've changed the SCLK above, we may need to update
508 * the UART divisors (UART baud rates are based on SCLK).
509 * Do the division by hand as there are no native instructions
510 * for dividing which means we'd generate a libgcc reference.
512 if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
514 unsigned int sdivR, vcoR;
515 sdivR = bfin_read_PLL_DIV() & 0xf;
516 vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
517 int dividend = sdivB * divB * vcoR;
518 int divisor = vcoB * sdivR;
519 unsigned int quotient;
520 for (quotient = 0; dividend > 0; ++quotient)
522 serial_early_put_div(quotient - ANOMALY_05000230);
529 __attribute__((always_inline)) static inline void
530 program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
534 if (!CONFIG_MEM_SIZE)
539 /* Program the external memory controller before we come out of
540 * self-refresh. This only works with our SDRAM controller.
543 # ifdef CONFIG_EBIU_SDRRC_VAL
544 bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
546 # ifdef CONFIG_EBIU_SDBCTL_VAL
547 bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
549 # ifdef CONFIG_EBIU_SDGCTL_VAL
550 bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
556 /* Now that we've reprogrammed, take things out of self refresh. */
558 #if defined(EBIU_RSTCTL)
559 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
560 #elif defined(EBIU_SDGCTL)
561 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS));
566 /* Our DDR controller sucks and cannot be programmed while in
567 * self-refresh. So we have to pull it out before programming.
570 # ifdef CONFIG_EBIU_RSTCTL_VAL
571 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
573 # ifdef CONFIG_EBIU_DDRCTL0_VAL
574 bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
576 # ifdef CONFIG_EBIU_DDRCTL1_VAL
577 bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
579 # ifdef CONFIG_EBIU_DDRCTL2_VAL
580 bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
582 # ifdef CONFIG_EBIU_DDRCTL3_VAL
583 /* default is disable, so don't need to force this */
584 bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
586 # ifdef CONFIG_EBIU_DDRQUE_VAL
587 bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | CONFIG_EBIU_DDRQUE_VAL);
594 __attribute__((always_inline)) static inline void
595 check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs)
599 if (!CONFIG_MEM_SIZE)
604 /* Are we coming out of hibernate (suspend to memory) ?
605 * The memory layout is:
606 * 0x0: hibernate magic for anomaly 307 (0xDEADBEEF)
607 * 0x4: return address
610 * SCKELOW is unreliable on older parts (anomaly 307)
612 if (ANOMALY_05000307 || vr_ctl & 0x8000) {
613 uint32_t *hibernate_magic = 0;
614 __builtin_bfin_ssync(); /* make sure memory controller is done */
615 if (hibernate_magic[0] == 0xDEADBEEF) {
617 bfin_write_EVT15(hibernate_magic[1]);
618 bfin_write_IMASK(EVT_IVG15);
619 __asm__ __volatile__ (
620 /* load reti early to avoid anomaly 281 */
622 /* clear hibernate magic */
624 /* load stack pointer */
626 /* lower ourselves from reset ivg to ivg15 */
630 : "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */)
639 __attribute__((always_inline)) static inline void
640 program_async_controller(ADI_BOOT_DATA *bs)
644 /* Program the async banks controller. */
645 bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
646 bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
647 bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
651 /* Not all parts have these additional MMRs. */
653 bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
656 # ifdef CONFIG_EBIU_MODE_VAL
657 bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
659 # ifdef CONFIG_EBIU_FCTL_VAL
660 bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
667 BOOTROM_CALLED_FUNC_ATTR
668 void initcode(ADI_BOOT_DATA *bs)
670 ADI_BOOT_DATA bootstruct_scratch;
672 /* Setup NMI handler before anything else */
673 program_nmi_handler();
679 /* If the bootstruct is NULL, then it's because we're loading
680 * dynamically and not via LDR (bootrom). So set the struct to
681 * some scratch space.
684 bs = &bootstruct_scratch;
687 bool put_into_srfs = maybe_self_refresh(bs);
690 uint sdivB, divB, vcoB;
691 program_early_devices(bs, &sdivB, &divB, &vcoB);
694 u16 vr_ctl = program_clocks(bs, put_into_srfs);
697 update_serial_clocks(bs, sdivB, divB, vcoB);
700 program_memory_controller(bs, put_into_srfs);
703 check_hibernation(bs, vr_ctl, put_into_srfs);
706 program_async_controller(bs);
708 #ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
710 /* Tell the bootrom where our entry point is so that it knows
711 * where to jump to when finishing processing the LDR. This
712 * allows us to avoid small jump blocks in the LDR, and also
713 * works around anomaly 05000389 (init address in external
714 * memory causes bootrom to trigger external addressing IVHW).
716 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
717 bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE);