2 * initcode.c - Initialize the processor. This is usually entails things
3 * like external memory, voltage regulators, etc... Note that this file
4 * cannot make any function calls as it may be executed all by itself by
5 * the Blackfin's bootrom in LDR format.
7 * Copyright (c) 2004-2011 Analog Devices Inc.
9 * Licensed under the GPL-2 or later.
12 #define BFIN_IN_INITCODE
15 #include <asm/blackfin.h>
16 #include <asm/mach-common/bits/bootrom.h>
17 #include <asm/mach-common/bits/core.h>
18 #include <asm/mach-common/bits/ebiu.h>
19 #include <asm/mach-common/bits/pll.h>
20 #include <asm/mach-common/bits/uart.h>
22 #define BUG() while (1) { asm volatile("emuexcpt;"); }
26 __attribute__((always_inline))
27 static inline void serial_init(void)
29 uint32_t uart_base = UART_DLL;
32 # ifdef BFIN_BOOT_UART_USE_RTS
33 # define BFIN_UART_USE_RTS 1
35 # define BFIN_UART_USE_RTS 0
37 if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
40 /* force RTS rather than relying on auto RTS */
41 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL);
43 /* Wait for the line to clear up. We cannot rely on UART
44 * registers as none of them reflect the status of the RSR.
45 * Instead, we'll sleep for ~10 bit times at 9600 baud.
46 * We can precalc things here by assuming boot values for
47 * PLL rather than loading registers and calculating.
48 * baud = SCLK / (16 ^ (1 - EDBO) * Divisor)
50 * Divisor = (SCLK / baud) / 16
51 * SCLK = baud * 16 * Divisor
52 * SCLK = (0x14 * CONFIG_CLKIN_HZ) / 5
53 * CCLK = (16 * Divisor * 5) * (9600 / 10)
54 * In reality, this will probably be just about 1 second delay,
55 * so assuming 9600 baud is OK (both as a very low and too high
56 * speed as this will buffer things enough).
58 #define _NUMBITS (10) /* how many bits to delay */
59 #define _LOWBAUD (9600) /* low baud rate */
60 #define _SCLK ((0x14 * CONFIG_CLKIN_HZ) / 5) /* SCLK based on PLL */
61 #define _DIVISOR ((_SCLK / _LOWBAUD) / 16) /* UART DLL/DLH */
62 #define _NUMINS (3) /* how many instructions in loop */
63 #define _CCLK (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS)
66 asm volatile("" : : : "memory");
70 if (BFIN_DEBUG_EARLY_SERIAL) {
71 int ucen = bfin_read16(&pUART->gctl) & UCEN;
72 serial_early_init(uart_base);
74 /* If the UART is off, that means we need to program
75 * the baud rate ourselves initially.
78 serial_early_set_baud(uart_base, CONFIG_BAUDRATE);
82 __attribute__((always_inline))
83 static inline void serial_deinit(void)
86 uint32_t uart_base = UART_DLL;
88 if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
89 /* clear forced RTS rather than relying on auto RTS */
90 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL);
95 __attribute__((always_inline))
96 static inline void serial_putc(char c)
98 uint32_t uart_base = UART_DLL;
100 if (!BFIN_DEBUG_EARLY_SERIAL)
106 bfin_write16(&pUART->thr, c);
108 while (!(bfin_read16(&pUART->lsr) & TEMT))
112 #include "initcode.h"
114 __attribute__((always_inline)) static inline void
115 program_nmi_handler(void)
119 /* Older bootroms don't create a dummy NMI handler,
120 * so make one ourselves ASAP in case it fires.
122 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS && !ANOMALY_05000219)
126 "%0 = RETS;" /* Save current RETS */
127 "CALL 1f;" /* Figure out current PC */
128 "RTN;" /* The simple NMI handler */
130 "%1 = RETS;" /* Load addr of NMI handler */
131 "RETS = %0;" /* Restore RETS */
132 "[%2] = %1;" /* Write NMI handler */
133 : "=r"(tmp1), "=r"(tmp2) : "ab"(EVT2)
137 /* Max SCLK can be 133MHz ... dividing that by (2*4) gives
138 * us a freq of 16MHz for SPI which should generally be
139 * slow enough for the slow reads the bootrom uses.
141 #if !defined(CONFIG_SPI_FLASH_SLOW_READ) && \
142 ((defined(__ADSPBF52x__) && __SILICON_REVISION__ >= 2) || \
143 (defined(__ADSPBF54x__) && __SILICON_REVISION__ >= 1))
144 # define BOOTROM_SUPPORTS_SPI_FAST_READ 1
146 # define BOOTROM_SUPPORTS_SPI_FAST_READ 0
148 #ifndef CONFIG_SPI_BAUD_INITBLOCK
149 # define CONFIG_SPI_BAUD_INITBLOCK (BOOTROM_SUPPORTS_SPI_FAST_READ ? 2 : 4)
152 # define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD
155 /* PLL_DIV defines */
156 #ifndef CONFIG_PLL_DIV_VAL
157 # if (CONFIG_CCLK_DIV == 1)
158 # define CONFIG_CCLK_ACT_DIV CCLK_DIV1
159 # elif (CONFIG_CCLK_DIV == 2)
160 # define CONFIG_CCLK_ACT_DIV CCLK_DIV2
161 # elif (CONFIG_CCLK_DIV == 4)
162 # define CONFIG_CCLK_ACT_DIV CCLK_DIV4
163 # elif (CONFIG_CCLK_DIV == 8)
164 # define CONFIG_CCLK_ACT_DIV CCLK_DIV8
166 # define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
168 # define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV)
171 #ifndef CONFIG_PLL_LOCKCNT_VAL
172 # define CONFIG_PLL_LOCKCNT_VAL 0x0300
175 #ifndef CONFIG_PLL_CTL_VAL
176 # define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF)
179 /* Make sure our voltage value is sane so we don't blow up! */
180 #ifndef CONFIG_VR_CTL_VAL
181 # define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
182 # if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__)
183 # define CCLK_VLEV_120 400000000
184 # define CCLK_VLEV_125 533000000
185 # elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
186 # define CCLK_VLEV_120 401000000
187 # define CCLK_VLEV_125 401000000
188 # elif defined(__ADSPBF561__)
189 # define CCLK_VLEV_120 300000000
190 # define CCLK_VLEV_125 501000000
192 # if BFIN_CCLK < CCLK_VLEV_120
193 # define CONFIG_VR_CTL_VLEV VLEV_120
194 # elif BFIN_CCLK < CCLK_VLEV_125
195 # define CONFIG_VR_CTL_VLEV VLEV_125
197 # define CONFIG_VR_CTL_VLEV VLEV_130
199 # if defined(__ADSPBF52x__) /* TBD; use default */
200 # undef CONFIG_VR_CTL_VLEV
201 # define CONFIG_VR_CTL_VLEV VLEV_110
202 # elif defined(__ADSPBF54x__) /* TBD; use default */
203 # undef CONFIG_VR_CTL_VLEV
204 # define CONFIG_VR_CTL_VLEV VLEV_120
205 # elif defined(__ADSPBF538__) || defined(__ADSPBF539__) /* TBD; use default */
206 # undef CONFIG_VR_CTL_VLEV
207 # define CONFIG_VR_CTL_VLEV VLEV_125
210 # ifdef CONFIG_BFIN_MAC
211 # define CONFIG_VR_CTL_CLKBUF CLKBUFOE
213 # define CONFIG_VR_CTL_CLKBUF 0
216 # if defined(__ADSPBF52x__)
217 # define CONFIG_VR_CTL_FREQ FREQ_1000
219 # define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000)
222 # define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
225 /* some parts do not have an on-chip voltage regulator */
226 #if defined(__ADSPBF51x__)
227 # define CONFIG_HAS_VR 0
228 # undef CONFIG_VR_CTL_VAL
229 # define CONFIG_VR_CTL_VAL 0
231 # define CONFIG_HAS_VR 1
236 /* Blackfin with SDRAM */
237 #ifndef CONFIG_EBIU_SDBCTL_VAL
238 # if CONFIG_MEM_SIZE == 16
239 # define CONFIG_EBSZ_VAL EBSZ_16
240 # elif CONFIG_MEM_SIZE == 32
241 # define CONFIG_EBSZ_VAL EBSZ_32
242 # elif CONFIG_MEM_SIZE == 64
243 # define CONFIG_EBSZ_VAL EBSZ_64
244 # elif CONFIG_MEM_SIZE == 128
245 # define CONFIG_EBSZ_VAL EBSZ_128
246 # elif CONFIG_MEM_SIZE == 256
247 # define CONFIG_EBSZ_VAL EBSZ_256
248 # elif CONFIG_MEM_SIZE == 512
249 # define CONFIG_EBSZ_VAL EBSZ_512
251 # error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_SIZE
253 # if CONFIG_MEM_ADD_WDTH == 8
254 # define CONFIG_EBCAW_VAL EBCAW_8
255 # elif CONFIG_MEM_ADD_WDTH == 9
256 # define CONFIG_EBCAW_VAL EBCAW_9
257 # elif CONFIG_MEM_ADD_WDTH == 10
258 # define CONFIG_EBCAW_VAL EBCAW_10
259 # elif CONFIG_MEM_ADD_WDTH == 11
260 # define CONFIG_EBCAW_VAL EBCAW_11
262 # error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_ADD_WDTH
264 # define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE)
269 /* Conflicting Column Address Widths Causes SDRAM Errors:
270 * EB2CAW and EB3CAW must be the same
273 # if ((CONFIG_EBIU_SDBCTL_VAL & 0x30000000) >> 8) != (CONFIG_EBIU_SDBCTL_VAL & 0x00300000)
274 # error "Anomaly 05000362: EB2CAW and EB3CAW must be the same"
278 __attribute__((always_inline)) static inline void
279 program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
283 /* Save the clock pieces that are used in baud rate calculation */
284 if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
286 *sdivB = bfin_read_PLL_DIV() & 0xf;
287 *vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
288 *divB = serial_early_get_div();
294 #ifdef CONFIG_HW_WATCHDOG
295 # ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
296 # define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
298 /* Program the watchdog with an initial timeout of ~20 seconds.
299 * Hopefully that should be long enough to load the u-boot LDR
300 * (from wherever) and then the common u-boot code can take over.
301 * In bypass mode, the start.S would have already set a much lower
302 * timeout, so don't clobber that.
304 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
306 bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
307 bfin_write_WDOG_CTL(0);
314 /* Blackfin bootroms use the SPI slow read opcode instead of the SPI
315 * fast read, so we need to slow down the SPI clock a lot more during
316 * boot. Once we switch over to u-boot's SPI flash driver, we'll
317 * increase the speed appropriately.
319 if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
321 if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4)
322 bs->dFlags |= BFLAG_FASTREAD;
323 bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
330 __attribute__((always_inline)) static inline bool
331 maybe_self_refresh(ADI_BOOT_DATA *bs)
335 if (!CONFIG_MEM_SIZE)
338 /* If external memory is enabled, put it into self refresh first. */
339 #if defined(EBIU_RSTCTL)
340 if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
342 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ);
345 #elif defined(EBIU_SDGCTL)
346 if (bfin_read_EBIU_SDBCTL() & EBE) {
348 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
358 __attribute__((always_inline)) static inline u16
359 program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
365 vr_ctl = bfin_read_VR_CTL();
369 /* If we're entering self refresh, make sure it has happened. */
371 #if defined(EBIU_RSTCTL)
372 while (!(bfin_read_EBIU_RSTCTL() & SRACK))
374 #elif defined(EBIU_SDGCTL)
375 while (!(bfin_read_EBIU_SDSTAT() & SDSRA))
383 /* With newer bootroms, we use the helper function to set up
384 * the memory controller. Older bootroms lacks such helpers
385 * so we do it ourselves.
387 if (!ANOMALY_05000386) {
390 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
391 ADI_SYSCTRL_VALUES memory_settings;
392 uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_LOCKCNT;
393 if (!ANOMALY_05000440)
394 actions |= SYSCTRL_PLLDIV;
396 actions |= SYSCTRL_VRCTL;
397 if (CONFIG_VR_CTL_VAL & FREQ_MASK)
398 actions |= SYSCTRL_INTVOLTAGE;
400 actions |= SYSCTRL_EXTVOLTAGE;
401 memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
403 actions |= SYSCTRL_EXTVOLTAGE;
404 memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
405 memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
406 memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
408 bfin_write_SIC_IWR1(0);
411 bfrom_SysControl(actions, &memory_settings, NULL);
413 if (ANOMALY_05000440)
414 bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
416 bfin_write_SIC_IWR1(-1);
419 bfin_write_SICA_IWR0(-1);
420 bfin_write_SICA_IWR1(-1);
426 /* Disable all peripheral wakeups except for the PLL event. */
428 bfin_write_SIC_IWR0(1);
429 bfin_write_SIC_IWR1(0);
431 bfin_write_SIC_IWR2(0);
433 #elif defined(SICA_IWR0)
434 bfin_write_SICA_IWR0(1);
435 bfin_write_SICA_IWR1(0);
437 bfin_write_SIC_IWR(1);
442 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
443 bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
447 /* Only reprogram when needed to avoid triggering unnecessary
448 * PLL relock sequences.
450 if (vr_ctl != CONFIG_VR_CTL_VAL) {
452 bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
459 bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
463 /* Only reprogram when needed to avoid triggering unnecessary
464 * PLL relock sequences.
466 if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
468 bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
475 /* Restore all peripheral wakeups. */
477 bfin_write_SIC_IWR0(-1);
478 bfin_write_SIC_IWR1(-1);
480 bfin_write_SIC_IWR2(-1);
482 #elif defined(SICA_IWR0)
483 bfin_write_SICA_IWR0(-1);
484 bfin_write_SICA_IWR1(-1);
486 bfin_write_SIC_IWR(-1);
497 __attribute__((always_inline)) static inline void
498 update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
502 /* Since we've changed the SCLK above, we may need to update
503 * the UART divisors (UART baud rates are based on SCLK).
504 * Do the division by hand as there are no native instructions
505 * for dividing which means we'd generate a libgcc reference.
507 if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
509 unsigned int sdivR, vcoR;
510 sdivR = bfin_read_PLL_DIV() & 0xf;
511 vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
512 int dividend = sdivB * divB * vcoR;
513 int divisor = vcoB * sdivR;
514 unsigned int quotient;
515 for (quotient = 0; dividend > 0; ++quotient)
517 serial_early_put_div(UART_DLL, quotient - ANOMALY_05000230);
524 __attribute__((always_inline)) static inline void
525 program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
529 if (!CONFIG_MEM_SIZE)
534 /* Program the external memory controller before we come out of
535 * self-refresh. This only works with our SDRAM controller.
538 # ifdef CONFIG_EBIU_SDRRC_VAL
539 bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
541 # ifdef CONFIG_EBIU_SDBCTL_VAL
542 bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
544 # ifdef CONFIG_EBIU_SDGCTL_VAL
545 bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
551 /* Now that we've reprogrammed, take things out of self refresh. */
553 #if defined(EBIU_RSTCTL)
554 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
555 #elif defined(EBIU_SDGCTL)
556 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS));
561 /* Our DDR controller sucks and cannot be programmed while in
562 * self-refresh. So we have to pull it out before programming.
565 # ifdef CONFIG_EBIU_RSTCTL_VAL
566 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
568 # ifdef CONFIG_EBIU_DDRCTL0_VAL
569 bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
571 # ifdef CONFIG_EBIU_DDRCTL1_VAL
572 bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
574 # ifdef CONFIG_EBIU_DDRCTL2_VAL
575 bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
577 # ifdef CONFIG_EBIU_DDRCTL3_VAL
578 /* default is disable, so don't need to force this */
579 bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
581 # ifdef CONFIG_EBIU_DDRQUE_VAL
582 bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | CONFIG_EBIU_DDRQUE_VAL);
589 __attribute__((always_inline)) static inline void
590 check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs)
594 if (!CONFIG_MEM_SIZE)
599 /* Are we coming out of hibernate (suspend to memory) ?
600 * The memory layout is:
601 * 0x0: hibernate magic for anomaly 307 (0xDEADBEEF)
602 * 0x4: return address
605 * SCKELOW is unreliable on older parts (anomaly 307)
607 if (ANOMALY_05000307 || vr_ctl & 0x8000) {
608 uint32_t *hibernate_magic = 0;
609 __builtin_bfin_ssync(); /* make sure memory controller is done */
610 if (hibernate_magic[0] == 0xDEADBEEF) {
612 bfin_write_EVT15(hibernate_magic[1]);
613 bfin_write_IMASK(EVT_IVG15);
614 __asm__ __volatile__ (
615 /* load reti early to avoid anomaly 281 */
617 /* clear hibernate magic */
619 /* load stack pointer */
621 /* lower ourselves from reset ivg to ivg15 */
625 : "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */)
634 BOOTROM_CALLED_FUNC_ATTR
635 void initcode(ADI_BOOT_DATA *bs)
637 ADI_BOOT_DATA bootstruct_scratch;
639 /* Setup NMI handler before anything else */
640 program_nmi_handler();
646 /* If the bootstruct is NULL, then it's because we're loading
647 * dynamically and not via LDR (bootrom). So set the struct to
648 * some scratch space.
651 bs = &bootstruct_scratch;
654 bool put_into_srfs = maybe_self_refresh(bs);
657 uint sdivB, divB, vcoB;
658 program_early_devices(bs, &sdivB, &divB, &vcoB);
661 u16 vr_ctl = program_clocks(bs, put_into_srfs);
664 update_serial_clocks(bs, sdivB, divB, vcoB);
667 program_memory_controller(bs, put_into_srfs);
670 check_hibernation(bs, vr_ctl, put_into_srfs);
673 program_async_controller(bs);
675 #ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
677 /* Tell the bootrom where our entry point is so that it knows
678 * where to jump to when finishing processing the LDR. This
679 * allows us to avoid small jump blocks in the LDR, and also
680 * works around anomaly 05000389 (init address in external
681 * memory causes bootrom to trigger external addressing IVHW).
683 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
684 bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE);