2 * initcode.c - Initialize the processor. This is usually entails things
3 * like external memory, voltage regulators, etc... Note that this file
4 * cannot make any function calls as it may be executed all by itself by
5 * the Blackfin's bootrom in LDR format.
7 * Copyright (c) 2004-2011 Analog Devices Inc.
9 * Licensed under the GPL-2 or later.
12 #define BFIN_IN_INITCODE
15 #include <asm/blackfin.h>
16 #include <asm/mach-common/bits/watchdog.h>
17 #include <asm/mach-common/bits/bootrom.h>
18 #include <asm/mach-common/bits/core.h>
19 #include <asm/serial.h>
21 #define BUG() while (1) asm volatile("emuexcpt;");
24 #include <asm/mach-common/bits/ebiu.h>
25 #include <asm/mach-common/bits/pll.h>
26 #else /* __ADSPBF60x__ */
27 #include <asm/mach-common/bits/cgu.h>
29 #define CONFIG_BFIN_GET_DCLK_M \
30 ((CONFIG_CLKIN_HZ*CONFIG_VCO_MULT)/(CONFIG_DCLK_DIV*1000000))
32 #ifndef CONFIG_DMC_DDRCFG
33 #if ((CONFIG_BFIN_GET_DCLK_M != 125) && \
34 (CONFIG_BFIN_GET_DCLK_M != 133) && \
35 (CONFIG_BFIN_GET_DCLK_M != 150) && \
36 (CONFIG_BFIN_GET_DCLK_M != 166) && \
37 (CONFIG_BFIN_GET_DCLK_M != 200) && \
38 (CONFIG_BFIN_GET_DCLK_M != 225) && \
39 (CONFIG_BFIN_GET_DCLK_M != 250))
40 #error "DDR2 CLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
44 /* DMC control bits */
49 #define MEMINITDONE 0x4
53 #define DLLCALDONE 0x2000
54 #define PENDREF 0xF0000
55 #define PHYRDPHASE 0xF00000
56 #define PHYRDPHASE_OFFSET 20
58 /* DMC DLL control bits */
59 #define DLLCALRDCNT 0xFF
60 #define DATACYC_OFFSET 8
73 static struct ddr_config ddr_config_table[] = {
75 .ddr_clk = 125, /* 125MHz */
76 .dmc_ddrctl = 0x00000904,
77 .dmc_ddrcfg = 0x00000422,
78 .dmc_ddrtr0 = 0x20705212,
79 .dmc_ddrtr1 = 0x201003CF,
80 .dmc_ddrtr2 = 0x00320107,
81 .dmc_ddrmr = 0x00000422,
85 .ddr_clk = 133, /* 133MHz */
86 .dmc_ddrctl = 0x00000904,
87 .dmc_ddrcfg = 0x00000422,
88 .dmc_ddrtr0 = 0x20806313,
89 .dmc_ddrtr1 = 0x2013040D,
90 .dmc_ddrtr2 = 0x00320108,
91 .dmc_ddrmr = 0x00000632,
95 .ddr_clk = 150, /* 150MHz */
96 .dmc_ddrctl = 0x00000904,
97 .dmc_ddrcfg = 0x00000422,
98 .dmc_ddrtr0 = 0x20A07323,
99 .dmc_ddrtr1 = 0x20160492,
100 .dmc_ddrtr2 = 0x00320209,
101 .dmc_ddrmr = 0x00000632,
105 .ddr_clk = 166, /* 166MHz */
106 .dmc_ddrctl = 0x00000904,
107 .dmc_ddrcfg = 0x00000422,
108 .dmc_ddrtr0 = 0x20A07323,
109 .dmc_ddrtr1 = 0x2016050E,
110 .dmc_ddrtr2 = 0x00320209,
111 .dmc_ddrmr = 0x00000632,
115 .ddr_clk = 200, /* 200MHz */
116 .dmc_ddrctl = 0x00000904,
117 .dmc_ddrcfg = 0x00000422,
118 .dmc_ddrtr0 = 0x20a07323,
119 .dmc_ddrtr1 = 0x2016050f,
120 .dmc_ddrtr2 = 0x00320509,
121 .dmc_ddrmr = 0x00000632,
125 .ddr_clk = 225, /* 225MHz */
126 .dmc_ddrctl = 0x00000904,
127 .dmc_ddrcfg = 0x00000422,
128 .dmc_ddrtr0 = 0x20E0A424,
129 .dmc_ddrtr1 = 0x302006DB,
130 .dmc_ddrtr2 = 0x0032020D,
131 .dmc_ddrmr = 0x00000842,
135 .ddr_clk = 250, /* 250MHz */
136 .dmc_ddrctl = 0x00000904,
137 .dmc_ddrcfg = 0x00000422,
138 .dmc_ddrtr0 = 0x20E0A424,
139 .dmc_ddrtr1 = 0x3020079E,
140 .dmc_ddrtr2 = 0x0032050D,
141 .dmc_ddrmr = 0x00000842,
145 #endif /* __ADSPBF60x__ */
147 __attribute__((always_inline))
148 static inline void serial_init(void)
150 uint32_t uart_base = UART_BASE;
152 #if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
153 # ifdef BFIN_BOOT_UART_USE_RTS
154 # define BFIN_UART_USE_RTS 1
156 # define BFIN_UART_USE_RTS 0
158 if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
161 /* force RTS rather than relying on auto RTS */
162 #if BFIN_UART_HW_VER < 4
163 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL);
165 bfin_write32(&pUART->control, bfin_read32(&pUART->control) |
169 /* Wait for the line to clear up. We cannot rely on UART
170 * registers as none of them reflect the status of the RSR.
171 * Instead, we'll sleep for ~10 bit times at 9600 baud.
172 * We can precalc things here by assuming boot values for
173 * PLL rather than loading registers and calculating.
174 * baud = SCLK / (16 ^ (1 - EDBO) * Divisor)
176 * Divisor = (SCLK / baud) / 16
177 * SCLK = baud * 16 * Divisor
178 * SCLK = (0x14 * CONFIG_CLKIN_HZ) / 5
179 * CCLK = (16 * Divisor * 5) * (9600 / 10)
180 * In reality, this will probably be just about 1 second delay,
181 * so assuming 9600 baud is OK (both as a very low and too high
182 * speed as this will buffer things enough).
184 #define _NUMBITS (10) /* how many bits to delay */
185 #define _LOWBAUD (9600) /* low baud rate */
186 #define _SCLK ((0x14 * CONFIG_CLKIN_HZ) / 5) /* SCLK based on PLL */
187 #define _DIVISOR ((_SCLK / _LOWBAUD) / 16) /* UART DLL/DLH */
188 #define _NUMINS (3) /* how many instructions in loop */
189 #define _CCLK (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS)
192 asm volatile("" : : : "memory");
196 #if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS
197 if (BFIN_DEBUG_EARLY_SERIAL) {
198 serial_early_init(uart_base);
199 serial_early_set_baud(uart_base, CONFIG_BAUDRATE);
204 __attribute__((always_inline))
205 static inline void serial_deinit(void)
207 #if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
208 uint32_t uart_base = UART_BASE;
210 if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
211 /* clear forced RTS rather than relying on auto RTS */
212 #if BFIN_UART_HW_VER < 4
213 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL);
215 bfin_write32(&pUART->control, bfin_read32(&pUART->control) &
222 __attribute__((always_inline))
223 static inline void serial_putc(char c)
225 uint32_t uart_base = UART_BASE;
227 if (!BFIN_DEBUG_EARLY_SERIAL)
233 bfin_write(&pUART->thr, c);
235 while (!(_lsr_read(pUART) & TEMT))
239 #include "initcode.h"
241 __attribute__((always_inline)) static inline void
242 program_nmi_handler(void)
246 /* Older bootroms don't create a dummy NMI handler,
247 * so make one ourselves ASAP in case it fires.
249 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS && !ANOMALY_05000219)
253 "%0 = RETS;" /* Save current RETS */
254 "CALL 1f;" /* Figure out current PC */
255 "RTN;" /* The simple NMI handler */
257 "%1 = RETS;" /* Load addr of NMI handler */
258 "RETS = %0;" /* Restore RETS */
259 "[%2] = %1;" /* Write NMI handler */
260 : "=d"(tmp1), "=d"(tmp2)
265 /* Max SCLK can be 133MHz ... dividing that by (2*4) gives
266 * us a freq of 16MHz for SPI which should generally be
267 * slow enough for the slow reads the bootrom uses.
269 #if !defined(CONFIG_SPI_FLASH_SLOW_READ) && \
270 ((defined(__ADSPBF52x__) && __SILICON_REVISION__ >= 2) || \
271 (defined(__ADSPBF54x__) && __SILICON_REVISION__ >= 1))
272 # define BOOTROM_SUPPORTS_SPI_FAST_READ 1
274 # define BOOTROM_SUPPORTS_SPI_FAST_READ 0
276 #ifndef CONFIG_SPI_BAUD_INITBLOCK
277 # define CONFIG_SPI_BAUD_INITBLOCK (BOOTROM_SUPPORTS_SPI_FAST_READ ? 2 : 4)
280 # define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD
285 #ifndef CONFIG_CGU_CTL_VAL
286 # define CONFIG_CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CONFIG_CLKIN_HALF)
289 #ifndef CONFIG_CGU_DIV_VAL
290 # define CONFIG_CGU_DIV_VAL \
291 ((CONFIG_CCLK_DIV << CSEL_P) | \
292 (CONFIG_SCLK0_DIV << S0SEL_P) | \
293 (CONFIG_SCLK_DIV << SYSSEL_P) | \
294 (CONFIG_SCLK1_DIV << S1SEL_P) | \
295 (CONFIG_DCLK_DIV << DSEL_P) | \
296 (CONFIG_OCLK_DIV << OSEL_P))
299 #else /* __ADSPBF60x__ */
301 /* PLL_DIV defines */
302 #ifndef CONFIG_PLL_DIV_VAL
303 # if (CONFIG_CCLK_DIV == 1)
304 # define CONFIG_CCLK_ACT_DIV CCLK_DIV1
305 # elif (CONFIG_CCLK_DIV == 2)
306 # define CONFIG_CCLK_ACT_DIV CCLK_DIV2
307 # elif (CONFIG_CCLK_DIV == 4)
308 # define CONFIG_CCLK_ACT_DIV CCLK_DIV4
309 # elif (CONFIG_CCLK_DIV == 8)
310 # define CONFIG_CCLK_ACT_DIV CCLK_DIV8
312 # define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
314 # define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV)
317 #ifndef CONFIG_PLL_LOCKCNT_VAL
318 # define CONFIG_PLL_LOCKCNT_VAL 0x0300
321 #ifndef CONFIG_PLL_CTL_VAL
322 # define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF)
325 /* Make sure our voltage value is sane so we don't blow up! */
326 #ifndef CONFIG_VR_CTL_VAL
327 # define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
328 # if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__)
329 # define CCLK_VLEV_120 400000000
330 # define CCLK_VLEV_125 533000000
331 # elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
332 # define CCLK_VLEV_120 401000000
333 # define CCLK_VLEV_125 401000000
334 # elif defined(__ADSPBF561__)
335 # define CCLK_VLEV_120 300000000
336 # define CCLK_VLEV_125 501000000
338 # if BFIN_CCLK < CCLK_VLEV_120
339 # define CONFIG_VR_CTL_VLEV VLEV_120
340 # elif BFIN_CCLK < CCLK_VLEV_125
341 # define CONFIG_VR_CTL_VLEV VLEV_125
343 # define CONFIG_VR_CTL_VLEV VLEV_130
345 # if defined(__ADSPBF52x__) /* TBD; use default */
346 # undef CONFIG_VR_CTL_VLEV
347 # define CONFIG_VR_CTL_VLEV VLEV_110
348 # elif defined(__ADSPBF54x__) /* TBD; use default */
349 # undef CONFIG_VR_CTL_VLEV
350 # define CONFIG_VR_CTL_VLEV VLEV_120
351 # elif defined(__ADSPBF538__) || defined(__ADSPBF539__) /* TBD; use default */
352 # undef CONFIG_VR_CTL_VLEV
353 # define CONFIG_VR_CTL_VLEV VLEV_125
356 # ifdef CONFIG_BFIN_MAC
357 # define CONFIG_VR_CTL_CLKBUF CLKBUFOE
359 # define CONFIG_VR_CTL_CLKBUF 0
362 # if defined(__ADSPBF52x__)
363 # define CONFIG_VR_CTL_FREQ FREQ_1000
365 # define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000)
368 # define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
371 /* some parts do not have an on-chip voltage regulator */
372 #if defined(__ADSPBF51x__)
373 # define CONFIG_HAS_VR 0
374 # undef CONFIG_VR_CTL_VAL
375 # define CONFIG_VR_CTL_VAL 0
377 # define CONFIG_HAS_VR 1
382 /* Blackfin with SDRAM */
383 #ifndef CONFIG_EBIU_SDBCTL_VAL
384 # if CONFIG_MEM_SIZE == 16
385 # define CONFIG_EBSZ_VAL EBSZ_16
386 # elif CONFIG_MEM_SIZE == 32
387 # define CONFIG_EBSZ_VAL EBSZ_32
388 # elif CONFIG_MEM_SIZE == 64
389 # define CONFIG_EBSZ_VAL EBSZ_64
390 # elif CONFIG_MEM_SIZE == 128
391 # define CONFIG_EBSZ_VAL EBSZ_128
392 # elif CONFIG_MEM_SIZE == 256
393 # define CONFIG_EBSZ_VAL EBSZ_256
394 # elif CONFIG_MEM_SIZE == 512
395 # define CONFIG_EBSZ_VAL EBSZ_512
397 # error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_SIZE
399 # if CONFIG_MEM_ADD_WDTH == 8
400 # define CONFIG_EBCAW_VAL EBCAW_8
401 # elif CONFIG_MEM_ADD_WDTH == 9
402 # define CONFIG_EBCAW_VAL EBCAW_9
403 # elif CONFIG_MEM_ADD_WDTH == 10
404 # define CONFIG_EBCAW_VAL EBCAW_10
405 # elif CONFIG_MEM_ADD_WDTH == 11
406 # define CONFIG_EBCAW_VAL EBCAW_11
408 # error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_ADD_WDTH
410 # define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE)
415 /* Conflicting Column Address Widths Causes SDRAM Errors:
416 * EB2CAW and EB3CAW must be the same
419 # if ((CONFIG_EBIU_SDBCTL_VAL & 0x30000000) >> 8) != (CONFIG_EBIU_SDBCTL_VAL & 0x00300000)
420 # error "Anomaly 05000362: EB2CAW and EB3CAW must be the same"
424 #endif /* __ADSPBF60x__ */
426 __attribute__((always_inline)) static inline void
427 program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
431 /* Save the clock pieces that are used in baud rate calculation */
432 if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
435 *sdivB = bfin_read_CGU_DIV();
436 *sdivB = ((*sdivB >> 8) & 0x1f) * ((*sdivB >> 5) & 0x7);
437 *vcoB = (bfin_read_CGU_CTL() >> 8) & 0x7f;
439 *sdivB = bfin_read_PLL_DIV() & 0xf;
440 *vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
442 *divB = serial_early_get_div();
448 #ifdef CONFIG_HW_WATCHDOG
449 # ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
450 # define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
452 /* Program the watchdog with an initial timeout of ~20 seconds.
453 * Hopefully that should be long enough to load the u-boot LDR
454 * (from wherever) and then the common u-boot code can take over.
455 * In bypass mode, the start.S would have already set a much lower
456 * timeout, so don't clobber that.
458 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
461 bfin_write_SEC_GCTL(0x2);
463 bfin_write_SEC_FCTL(0xc1);
464 bfin_write_SEC_SCTL(2, bfin_read_SEC_SCTL(2) | 0x6);
466 bfin_write_SEC_CCTL(0x2);
468 bfin_write_SEC_GCTL(0x1);
469 bfin_write_SEC_CCTL(0x1);
471 bfin_write_WDOG_CTL(WDDIS);
473 bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
474 #if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART
475 bfin_write_WDOG_CTL(WDEN);
483 /* Blackfin bootroms use the SPI slow read opcode instead of the SPI
484 * fast read, so we need to slow down the SPI clock a lot more during
485 * boot. Once we switch over to u-boot's SPI flash driver, we'll
486 * increase the speed appropriately.
489 if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
491 if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4)
492 bs->dFlags |= BFLAG_FASTREAD;
493 bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
501 __attribute__((always_inline)) static inline bool
502 maybe_self_refresh(ADI_BOOT_DATA *bs)
506 if (!CONFIG_MEM_SIZE)
510 /* resume from hibernate, return false let ddr initialize */
511 if ((bfin_read32(DPM0_STAT) & 0xF0) == 0x50) {
516 #else /* __ADSPBF60x__ */
518 /* If external memory is enabled, put it into self refresh first. */
519 #if defined(EBIU_RSTCTL)
520 if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
522 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ);
525 #elif defined(EBIU_SDGCTL)
526 if (bfin_read_EBIU_SDBCTL() & EBE) {
528 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
533 #endif /* __ADSPBF60x__ */
539 __attribute__((always_inline)) static inline u16
540 program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
547 if (bfin_read_DMC0_STAT() & MEMINITDONE) {
548 bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ);
550 while (!(bfin_read_DMC0_STAT() & SRACK))
554 /* Don't set the same value of MSEL and DF to CGU_CTL */
555 if ((bfin_read_CGU_CTL() & (MSEL_MASK | DF_MASK))
556 != CONFIG_CGU_CTL_VAL) {
557 bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL);
558 bfin_write_CGU_CTL(CONFIG_CGU_CTL_VAL);
559 while ((bfin_read_CGU_STAT() & (CLKSALGN | PLLBP)) ||
560 !(bfin_read_CGU_STAT() & PLLLK))
564 bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL | UPDT);
565 while (bfin_read_CGU_STAT() & CLKSALGN)
568 if (bfin_read_DMC0_STAT() & MEMINITDONE) {
569 bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ);
571 while (bfin_read_DMC0_STAT() & SRACK)
575 #else /* __ADSPBF60x__ */
577 vr_ctl = bfin_read_VR_CTL();
581 /* If we're entering self refresh, make sure it has happened. */
583 #if defined(EBIU_RSTCTL)
584 while (!(bfin_read_EBIU_RSTCTL() & SRACK))
586 #elif defined(EBIU_SDGCTL)
587 while (!(bfin_read_EBIU_SDSTAT() & SDSRA))
595 /* With newer bootroms, we use the helper function to set up
596 * the memory controller. Older bootroms lacks such helpers
597 * so we do it ourselves.
599 if (!ANOMALY_05000386) {
602 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
603 ADI_SYSCTRL_VALUES memory_settings;
604 uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_LOCKCNT;
605 if (!ANOMALY_05000440)
606 actions |= SYSCTRL_PLLDIV;
608 actions |= SYSCTRL_VRCTL;
609 if (CONFIG_VR_CTL_VAL & FREQ_MASK)
610 actions |= SYSCTRL_INTVOLTAGE;
612 actions |= SYSCTRL_EXTVOLTAGE;
613 memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
615 actions |= SYSCTRL_EXTVOLTAGE;
616 memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
617 memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
618 memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
620 bfin_write_SIC_IWR1(0);
623 bfrom_SysControl(actions, &memory_settings, NULL);
625 if (ANOMALY_05000440)
626 bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
628 bfin_write_SIC_IWR1(-1);
631 bfin_write_SICA_IWR0(-1);
632 bfin_write_SICA_IWR1(-1);
638 /* Disable all peripheral wakeups except for the PLL event. */
640 bfin_write_SIC_IWR0(1);
641 bfin_write_SIC_IWR1(0);
643 bfin_write_SIC_IWR2(0);
645 #elif defined(SICA_IWR0)
646 bfin_write_SICA_IWR0(1);
647 bfin_write_SICA_IWR1(0);
648 #elif defined(SIC_IWR)
649 bfin_write_SIC_IWR(1);
654 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
655 bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
659 /* Only reprogram when needed to avoid triggering unnecessary
660 * PLL relock sequences.
662 if (vr_ctl != CONFIG_VR_CTL_VAL) {
664 bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
671 bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
675 /* Only reprogram when needed to avoid triggering unnecessary
676 * PLL relock sequences.
678 if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
680 bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
687 /* Restore all peripheral wakeups. */
689 bfin_write_SIC_IWR0(-1);
690 bfin_write_SIC_IWR1(-1);
692 bfin_write_SIC_IWR2(-1);
694 #elif defined(SICA_IWR0)
695 bfin_write_SICA_IWR0(-1);
696 bfin_write_SICA_IWR1(-1);
697 #elif defined(SIC_IWR)
698 bfin_write_SIC_IWR(-1);
704 #endif /* __ADSPBF60x__ */
711 __attribute__((always_inline)) static inline void
712 update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
714 /* Since we've changed the SCLK above, we may need to update
715 * the UART divisors (UART baud rates are based on SCLK).
716 * Do the division by hand as there are no native instructions
717 * for dividing which means we'd generate a libgcc reference.
719 unsigned int sdivR, vcoR;
720 unsigned int dividend;
721 unsigned int divisor;
722 unsigned int quotient;
727 sdivR = bfin_read_CGU_DIV();
728 sdivR = ((sdivR >> 8) & 0x1f) * ((sdivR >> 5) & 0x7);
729 vcoR = (bfin_read_CGU_CTL() >> 8) & 0x7f;
731 sdivR = bfin_read_PLL_DIV() & 0xf;
732 vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
735 dividend = sdivB * divB * vcoR;
736 divisor = vcoB * sdivR;
737 quotient = early_division(dividend, divisor);
738 serial_early_put_div(quotient - ANOMALY_05000230);
742 __attribute__((always_inline)) static inline void
743 program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
747 if (!CONFIG_MEM_SIZE)
757 if (CONFIG_BFIN_GET_DCLK_M == 125)
759 else if (CONFIG_BFIN_GET_DCLK_M == 133)
761 else if (CONFIG_BFIN_GET_DCLK_M == 150)
763 else if (CONFIG_BFIN_GET_DCLK_M == 166)
765 else if (CONFIG_BFIN_GET_DCLK_M == 200)
767 else if (CONFIG_BFIN_GET_DCLK_M == 225)
769 else if (CONFIG_BFIN_GET_DCLK_M == 250)
773 for (i = 0; i < ARRAY_SIZE(ddr_config_table); i++)
774 if (CONFIG_BFIN_GET_DCLK_M == ddr_config_table[i].ddr_clk)
778 #ifndef CONFIG_DMC_DDRCFG
779 bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg);
781 bfin_write_DMC0_CFG(CONFIG_DMC_DDRCFG);
783 #ifndef CONFIG_DMC_DDRTR0
784 bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0);
786 bfin_write_DMC0_TR0(CONFIG_DMC_DDRTR0);
788 #ifndef CONFIG_DMC_DDRTR1
789 bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1);
791 bfin_write_DMC0_TR1(CONFIG_DMC_DDRTR1);
793 #ifndef CONFIG_DMC_DDRTR2
794 bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2);
796 bfin_write_DMC0_TR2(CONFIG_DMC_DDRTR2);
798 #ifndef CONFIG_DMC_DDRMR
799 bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr);
801 bfin_write_DMC0_MR(CONFIG_DMC_DDRMR);
803 #ifndef CONFIG_DMC_DDREMR1
804 bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1);
806 bfin_write_DMC0_EMR1(CONFIG_DMC_DDREMR1);
808 #ifndef CONFIG_DMC_DDRCTL
809 bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl);
811 bfin_write_DMC0_CTL(CONFIG_DMC_DDRCTL);
815 while (!(bfin_read_DMC0_STAT() & MEMINITDONE))
818 dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >>
820 dll_ctl = bfin_read_DMC0_DLLCTL();
822 bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET));
825 while (!(bfin_read_DMC0_STAT() & DLLCALDONE))
829 #else /* __ADSPBF60x__ */
831 /* Program the external memory controller before we come out of
832 * self-refresh. This only works with our SDRAM controller.
835 # ifdef CONFIG_EBIU_SDRRC_VAL
836 bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
838 # ifdef CONFIG_EBIU_SDBCTL_VAL
839 bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
841 # ifdef CONFIG_EBIU_SDGCTL_VAL
842 bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
848 /* Now that we've reprogrammed, take things out of self refresh. */
850 #if defined(EBIU_RSTCTL)
851 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
852 #elif defined(EBIU_SDGCTL)
853 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS));
858 /* Our DDR controller sucks and cannot be programmed while in
859 * self-refresh. So we have to pull it out before programming.
862 # ifdef CONFIG_EBIU_RSTCTL_VAL
863 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
865 # ifdef CONFIG_EBIU_DDRCTL0_VAL
866 bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
868 # ifdef CONFIG_EBIU_DDRCTL1_VAL
869 bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
871 # ifdef CONFIG_EBIU_DDRCTL2_VAL
872 bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
874 # ifdef CONFIG_EBIU_DDRCTL3_VAL
875 /* default is disable, so don't need to force this */
876 bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
878 # ifdef CONFIG_EBIU_DDRQUE_VAL
879 bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | CONFIG_EBIU_DDRQUE_VAL);
883 #endif /* __ADSPBF60x__ */
887 __attribute__((always_inline)) static inline void
888 check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs)
892 if (!CONFIG_MEM_SIZE)
897 if (bfin_read32(DPM0_RESTORE0) != 0) {
898 uint32_t reg = bfin_read_DMC0_CTL();
900 bfin_write_DMC0_CTL(reg);
902 while ((bfin_read_DMC0_STAT() & 0x8))
904 while (!(bfin_read_DMC0_STAT() & 0x1))
908 uint32_t *hibernate_magic = bfin_read32(DPM0_RESTORE4);
909 SSYNC(); /* make sure memory controller is done */
910 if (hibernate_magic[0] == 0xDEADBEEF) {
913 bfin_write_EVT15(hibernate_magic[1]);
914 bfin_write_IMASK(EVT_IVG15);
915 __asm__ __volatile__ (
916 /* load reti early to avoid anomaly 281 */
918 /* clear hibernate magic */
920 /* load stack pointer */
922 /* lower ourselves from reset ivg to ivg15 */
927 : "p"(hibernate_magic),
928 "d"(0x2000 /* jump.s 0 */),
936 /* Are we coming out of hibernate (suspend to memory) ?
937 * The memory layout is:
938 * 0x0: hibernate magic for anomaly 307 (0xDEADBEEF)
939 * 0x4: return address
942 * SCKELOW is unreliable on older parts (anomaly 307)
944 if (ANOMALY_05000307 || vr_ctl & 0x8000) {
945 uint32_t *hibernate_magic = 0;
948 if (hibernate_magic[0] == 0xDEADBEEF) {
950 bfin_write_EVT15(hibernate_magic[1]);
951 bfin_write_IMASK(EVT_IVG15);
952 __asm__ __volatile__ (
953 /* load reti early to avoid anomaly 281 */
955 /* clear hibernate magic */
957 /* load stack pointer */
959 /* lower ourselves from reset ivg to ivg15 */
963 : "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */)
973 BOOTROM_CALLED_FUNC_ATTR
974 void initcode(ADI_BOOT_DATA *bs)
976 ADI_BOOT_DATA bootstruct_scratch;
978 /* Setup NMI handler before anything else */
979 program_nmi_handler();
985 /* If the bootstruct is NULL, then it's because we're loading
986 * dynamically and not via LDR (bootrom). So set the struct to
987 * some scratch space.
990 bs = &bootstruct_scratch;
993 bool put_into_srfs = maybe_self_refresh(bs);
996 uint sdivB, divB, vcoB;
997 program_early_devices(bs, &sdivB, &divB, &vcoB);
1000 u16 vr_ctl = program_clocks(bs, put_into_srfs);
1003 update_serial_clocks(bs, sdivB, divB, vcoB);
1006 program_memory_controller(bs, put_into_srfs);
1009 check_hibernation(bs, vr_ctl, put_into_srfs);
1012 program_async_controller(bs);
1014 #ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
1016 /* Tell the bootrom where our entry point is so that it knows
1017 * where to jump to when finishing processing the LDR. This
1018 * allows us to avoid small jump blocks in the LDR, and also
1019 * works around anomaly 05000389 (init address in external
1020 * memory causes bootrom to trigger external addressing IVHW).
1022 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
1023 bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE);