git.sur5r.net Git - u-boot/blob - arch/blackfin/cpu/initcode.c

   1 /*
   2  * initcode.c - Initialize the processor.  This is usually entails things
   3  * like external memory, voltage regulators, etc...  Note that this file
   4  * cannot make any function calls as it may be executed all by itself by
   5  * the Blackfin's bootrom in LDR format.
   6  *
   7  * Copyright (c) 2004-2011 Analog Devices Inc.
   8  *
   9  * Licensed under the GPL-2 or later.
  10  */
  11
  12 #define BFIN_IN_INITCODE
  13
  14 #include <config.h>
  15 #include <asm/blackfin.h>
  16 #include <asm/mach-common/bits/watchdog.h>
  17 #include <asm/mach-common/bits/bootrom.h>
  18 #include <asm/mach-common/bits/core.h>
  19
  20 #define BUG() while (1) { asm volatile("emuexcpt;"); }
  21
  22 #include "serial.h"
  23
  24 #ifndef __ADSPBF60x__
  25 #include <asm/mach-common/bits/ebiu.h>
  26 #include <asm/mach-common/bits/pll.h>
  27 #else /* __ADSPBF60x__ */
  28 #include <asm/mach-common/bits/cgu.h>
  29
  30 #define CONFIG_BFIN_GET_DCLK_M \
  31         ((CONFIG_CLKIN_HZ*CONFIG_VCO_MULT)/(CONFIG_DCLK_DIV*1000000))
  32
  33 #ifndef CONFIG_DMC_DDRCFG
  34 #if ((CONFIG_BFIN_GET_DCLK_M != 125) && \
  35         (CONFIG_BFIN_GET_DCLK_M != 133) && \
  36         (CONFIG_BFIN_GET_DCLK_M != 150) && \
  37         (CONFIG_BFIN_GET_DCLK_M != 166) && \
  38         (CONFIG_BFIN_GET_DCLK_M != 200) && \
  39         (CONFIG_BFIN_GET_DCLK_M != 225) && \
  40         (CONFIG_BFIN_GET_DCLK_M != 250))
  41 #error "DDR2 CLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
  42 #endif
  43 #endif
  44
  45 /* DMC control bits */
  46 #define SRREQ                   0x8
  47
  48 /* DMC status bits */
  49 #define IDLE                    0x1
  50 #define MEMINITDONE             0x4
  51 #define SRACK                   0x8
  52 #define PDACK                   0x10
  53 #define DPDACK                  0x20
  54 #define DLLCALDONE              0x2000
  55 #define PENDREF                 0xF0000
  56 #define PHYRDPHASE              0xF00000
  57 #define PHYRDPHASE_OFFSET       20
  58
  59 /* DMC DLL control bits */
  60 #define DLLCALRDCNT             0xFF
  61 #define DATACYC_OFFSET          8
  62
  63 struct ddr_config {
  64         u32 ddr_clk;
  65         u32 dmc_ddrctl;
  66         u32 dmc_ddrcfg;
  67         u32 dmc_ddrtr0;
  68         u32 dmc_ddrtr1;
  69         u32 dmc_ddrtr2;
  70         u32 dmc_ddrmr;
  71         u32 dmc_ddrmr1;
  72 };
  73
  74 static struct ddr_config ddr_config_table[] = {
  75         [0] = {
  76                 .ddr_clk    = 125,      /* 125MHz */
  77                 .dmc_ddrctl = 0x00000904,
  78                 .dmc_ddrcfg = 0x00000422,
  79                 .dmc_ddrtr0 = 0x20705212,
  80                 .dmc_ddrtr1 = 0x201003CF,
  81                 .dmc_ddrtr2 = 0x00320107,
  82                 .dmc_ddrmr  = 0x00000422,
  83                 .dmc_ddrmr1 = 0x4,
  84         },
  85         [1] = {
  86                 .ddr_clk    = 133,      /* 133MHz */
  87                 .dmc_ddrctl = 0x00000904,
  88                 .dmc_ddrcfg = 0x00000422,
  89                 .dmc_ddrtr0 = 0x20806313,
  90                 .dmc_ddrtr1 = 0x2013040D,
  91                 .dmc_ddrtr2 = 0x00320108,
  92                 .dmc_ddrmr  = 0x00000632,
  93                 .dmc_ddrmr1 = 0x4,
  94         },
  95         [2] = {
  96                 .ddr_clk    = 150,      /* 150MHz */
  97                 .dmc_ddrctl = 0x00000904,
  98                 .dmc_ddrcfg = 0x00000422,
  99                 .dmc_ddrtr0 = 0x20A07323,
 100                 .dmc_ddrtr1 = 0x20160492,
 101                 .dmc_ddrtr2 = 0x00320209,
 102                 .dmc_ddrmr  = 0x00000632,
 103                 .dmc_ddrmr1 = 0x4,
 104         },
 105         [3] = {
 106                 .ddr_clk    = 166,      /* 166MHz */
 107                 .dmc_ddrctl = 0x00000904,
 108                 .dmc_ddrcfg = 0x00000422,
 109                 .dmc_ddrtr0 = 0x20A07323,
 110                 .dmc_ddrtr1 = 0x2016050E,
 111                 .dmc_ddrtr2 = 0x00320209,
 112                 .dmc_ddrmr  = 0x00000632,
 113                 .dmc_ddrmr1 = 0x4,
 114         },
 115         [4] = {
 116                 .ddr_clk    = 200,      /* 200MHz */
 117                 .dmc_ddrctl = 0x00000904,
 118                 .dmc_ddrcfg = 0x00000422,
 119                 .dmc_ddrtr0 = 0x20a07323,
 120                 .dmc_ddrtr1 = 0x2016050f,
 121                 .dmc_ddrtr2 = 0x00320509,
 122                 .dmc_ddrmr  = 0x00000632,
 123                 .dmc_ddrmr1 = 0x4,
 124         },
 125         [5] = {
 126                 .ddr_clk    = 225,      /* 225MHz */
 127                 .dmc_ddrctl = 0x00000904,
 128                 .dmc_ddrcfg = 0x00000422,
 129                 .dmc_ddrtr0 = 0x20E0A424,
 130                 .dmc_ddrtr1 = 0x302006DB,
 131                 .dmc_ddrtr2 = 0x0032020D,
 132                 .dmc_ddrmr  = 0x00000842,
 133                 .dmc_ddrmr1 = 0x4,
 134         },
 135         [6] = {
 136                 .ddr_clk    = 250,      /* 250MHz */
 137                 .dmc_ddrctl = 0x00000904,
 138                 .dmc_ddrcfg = 0x00000422,
 139                 .dmc_ddrtr0 = 0x20E0A424,
 140                 .dmc_ddrtr1 = 0x3020079E,
 141                 .dmc_ddrtr2 = 0x0032050D,
 142                 .dmc_ddrmr  = 0x00000842,
 143                 .dmc_ddrmr1 = 0x4,
 144         },
 145 };
 146 #endif /* __ADSPBF60x__ */
 147
 148 __attribute__((always_inline))
 149 static inline void serial_init(void)
 150 {
 151         uint32_t uart_base = UART_BASE;
 152
 153 #if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
 154 # ifdef BFIN_BOOT_UART_USE_RTS
 155 #  define BFIN_UART_USE_RTS 1
 156 # else
 157 #  define BFIN_UART_USE_RTS 0
 158 # endif
 159         if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
 160                 size_t i;
 161
 162                 /* force RTS rather than relying on auto RTS */
 163 #if BFIN_UART_HW_VER < 4
 164                 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL);
 165 #else
 166                 bfin_write32(&pUART->control, bfin_read32(&pUART->control) |
 167                                 FCPOL);
 168 #endif
 169
 170                 /* Wait for the line to clear up.  We cannot rely on UART
 171                  * registers as none of them reflect the status of the RSR.
 172                  * Instead, we'll sleep for ~10 bit times at 9600 baud.
 173                  * We can precalc things here by assuming boot values for
 174                  * PLL rather than loading registers and calculating.
 175                  *      baud    = SCLK / (16 ^ (1 - EDBO) * Divisor)
 176                  *      EDB0    = 0
 177                  *      Divisor = (SCLK / baud) / 16
 178                  *      SCLK    = baud * 16 * Divisor
 179                  *      SCLK    = (0x14 * CONFIG_CLKIN_HZ) / 5
 180                  *      CCLK    = (16 * Divisor * 5) * (9600 / 10)
 181                  * In reality, this will probably be just about 1 second delay,
 182                  * so assuming 9600 baud is OK (both as a very low and too high
 183                  * speed as this will buffer things enough).
 184                  */
 185 #define _NUMBITS (10)                                   /* how many bits to delay */
 186 #define _LOWBAUD (9600)                                 /* low baud rate */
 187 #define _SCLK    ((0x14 * CONFIG_CLKIN_HZ) / 5)         /* SCLK based on PLL */
 188 #define _DIVISOR ((_SCLK / _LOWBAUD) / 16)              /* UART DLL/DLH */
 189 #define _NUMINS  (3)                                    /* how many instructions in loop */
 190 #define _CCLK    (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS)
 191                 i = _CCLK;
 192                 while (i--)
 193                         asm volatile("" : : : "memory");
 194         }
 195 #endif
 196
 197 #if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS
 198         if (BFIN_DEBUG_EARLY_SERIAL) {
 199                 serial_early_init(uart_base);
 200                 serial_early_set_baud(uart_base, CONFIG_BAUDRATE);
 201         }
 202 #endif
 203 }
 204
 205 __attribute__((always_inline))
 206 static inline void serial_deinit(void)
 207 {
 208 #if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
 209         uint32_t uart_base = UART_BASE;
 210
 211         if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
 212                 /* clear forced RTS rather than relying on auto RTS */
 213 #if BFIN_UART_HW_VER < 4
 214                 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL);
 215 #else
 216                 bfin_write32(&pUART->control, bfin_read32(&pUART->control) &
 217                                 ~FCPOL);
 218 #endif
 219         }
 220 #endif
 221 }
 222
 223 __attribute__((always_inline))
 224 static inline void serial_putc(char c)
 225 {
 226         uint32_t uart_base = UART_BASE;
 227
 228         if (!BFIN_DEBUG_EARLY_SERIAL)
 229                 return;
 230
 231         if (c == '\n')
 232                 serial_putc('\r');
 233
 234         bfin_write(&pUART->thr, c);
 235
 236         while (!(_lsr_read(pUART) & TEMT))
 237                 continue;
 238 }
 239
 240 #include "initcode.h"
 241
 242 __attribute__((always_inline)) static inline void
 243 program_nmi_handler(void)
 244 {
 245         u32 tmp1, tmp2;
 246
 247         /* Older bootroms don't create a dummy NMI handler,
 248          * so make one ourselves ASAP in case it fires.
 249          */
 250         if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS && !ANOMALY_05000219)
 251                 return;
 252
 253         asm volatile (
 254                 "%0 = RETS;" /* Save current RETS */
 255                 "CALL 1f;"   /* Figure out current PC */
 256                 "RTN;"       /* The simple NMI handler */
 257                 "1:"
 258                 "%1 = RETS;" /* Load addr of NMI handler */
 259                 "RETS = %0;" /* Restore RETS */
 260                 "[%2] = %1;" /* Write NMI handler */
 261                 : "=d"(tmp1), "=d"(tmp2)
 262                 : "ab"(EVT2)
 263         );
 264 }
 265
 266 /* Max SCLK can be 133MHz ... dividing that by (2*4) gives
 267  * us a freq of 16MHz for SPI which should generally be
 268  * slow enough for the slow reads the bootrom uses.
 269  */
 270 #if !defined(CONFIG_SPI_FLASH_SLOW_READ) && \
 271     ((defined(__ADSPBF52x__) && __SILICON_REVISION__ >= 2) || \
 272      (defined(__ADSPBF54x__) && __SILICON_REVISION__ >= 1))
 273 # define BOOTROM_SUPPORTS_SPI_FAST_READ 1
 274 #else
 275 # define BOOTROM_SUPPORTS_SPI_FAST_READ 0
 276 #endif
 277 #ifndef CONFIG_SPI_BAUD_INITBLOCK
 278 # define CONFIG_SPI_BAUD_INITBLOCK (BOOTROM_SUPPORTS_SPI_FAST_READ ? 2 : 4)
 279 #endif
 280 #ifdef SPI0_BAUD
 281 # define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD
 282 #endif
 283
 284 #ifdef __ADSPBF60x__
 285
 286 #ifndef CONFIG_CGU_CTL_VAL
 287 # define CONFIG_CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CONFIG_CLKIN_HALF)
 288 #endif
 289
 290 #ifndef CONFIG_CGU_DIV_VAL
 291 # define CONFIG_CGU_DIV_VAL \
 292         ((CONFIG_CCLK_DIV   << CSEL_P)   | \
 293          (CONFIG_SCLK0_DIV  << S0SEL_P)  | \
 294          (CONFIG_SCLK_DIV << SYSSEL_P) | \
 295          (CONFIG_SCLK1_DIV  << S1SEL_P)  | \
 296          (CONFIG_DCLK_DIV   << DSEL_P)   | \
 297          (CONFIG_OCLK_DIV   << OSEL_P))
 298 #endif
 299
 300 #else /* __ADSPBF60x__ */
 301
 302 /* PLL_DIV defines */
 303 #ifndef CONFIG_PLL_DIV_VAL
 304 # if (CONFIG_CCLK_DIV == 1)
 305 #  define CONFIG_CCLK_ACT_DIV CCLK_DIV1
 306 # elif (CONFIG_CCLK_DIV == 2)
 307 #  define CONFIG_CCLK_ACT_DIV CCLK_DIV2
 308 # elif (CONFIG_CCLK_DIV == 4)
 309 #  define CONFIG_CCLK_ACT_DIV CCLK_DIV4
 310 # elif (CONFIG_CCLK_DIV == 8)
 311 #  define CONFIG_CCLK_ACT_DIV CCLK_DIV8
 312 # else
 313 #  define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
 314 # endif
 315 # define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV)
 316 #endif
 317
 318 #ifndef CONFIG_PLL_LOCKCNT_VAL
 319 # define CONFIG_PLL_LOCKCNT_VAL 0x0300
 320 #endif
 321
 322 #ifndef CONFIG_PLL_CTL_VAL
 323 # define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF)
 324 #endif
 325
 326 /* Make sure our voltage value is sane so we don't blow up! */
 327 #ifndef CONFIG_VR_CTL_VAL
 328 # define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
 329 # if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__)
 330 #  define CCLK_VLEV_120 400000000
 331 #  define CCLK_VLEV_125 533000000
 332 # elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
 333 #  define CCLK_VLEV_120 401000000
 334 #  define CCLK_VLEV_125 401000000
 335 # elif defined(__ADSPBF561__)
 336 #  define CCLK_VLEV_120 300000000
 337 #  define CCLK_VLEV_125 501000000
 338 # endif
 339 # if BFIN_CCLK < CCLK_VLEV_120
 340 #  define CONFIG_VR_CTL_VLEV VLEV_120
 341 # elif BFIN_CCLK < CCLK_VLEV_125
 342 #  define CONFIG_VR_CTL_VLEV VLEV_125
 343 # else
 344 #  define CONFIG_VR_CTL_VLEV VLEV_130
 345 # endif
 346 # if defined(__ADSPBF52x__)     /* TBD; use default */
 347 #  undef CONFIG_VR_CTL_VLEV
 348 #  define CONFIG_VR_CTL_VLEV VLEV_110
 349 # elif defined(__ADSPBF54x__)   /* TBD; use default */
 350 #  undef CONFIG_VR_CTL_VLEV
 351 #  define CONFIG_VR_CTL_VLEV VLEV_120
 352 # elif defined(__ADSPBF538__) || defined(__ADSPBF539__) /* TBD; use default */
 353 #  undef CONFIG_VR_CTL_VLEV
 354 #  define CONFIG_VR_CTL_VLEV VLEV_125
 355 # endif
 356
 357 # ifdef CONFIG_BFIN_MAC
 358 #  define CONFIG_VR_CTL_CLKBUF CLKBUFOE
 359 # else
 360 #  define CONFIG_VR_CTL_CLKBUF 0
 361 # endif
 362
 363 # if defined(__ADSPBF52x__)
 364 #  define CONFIG_VR_CTL_FREQ FREQ_1000
 365 # else
 366 #  define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000)
 367 # endif
 368
 369 # define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
 370 #endif
 371
 372 /* some parts do not have an on-chip voltage regulator */
 373 #if defined(__ADSPBF51x__)
 374 # define CONFIG_HAS_VR 0
 375 # undef CONFIG_VR_CTL_VAL
 376 # define CONFIG_VR_CTL_VAL 0
 377 #else
 378 # define CONFIG_HAS_VR 1
 379 #endif
 380
 381 #if CONFIG_MEM_SIZE
 382 #ifndef EBIU_RSTCTL
 383 /* Blackfin with SDRAM */
 384 #ifndef CONFIG_EBIU_SDBCTL_VAL
 385 # if CONFIG_MEM_SIZE == 16
 386 #  define CONFIG_EBSZ_VAL EBSZ_16
 387 # elif CONFIG_MEM_SIZE == 32
 388 #  define CONFIG_EBSZ_VAL EBSZ_32
 389 # elif CONFIG_MEM_SIZE == 64
 390 #  define CONFIG_EBSZ_VAL EBSZ_64
 391 # elif CONFIG_MEM_SIZE == 128
 392 #  define CONFIG_EBSZ_VAL EBSZ_128
 393 # elif CONFIG_MEM_SIZE == 256
 394 #  define CONFIG_EBSZ_VAL EBSZ_256
 395 # elif CONFIG_MEM_SIZE == 512
 396 #  define CONFIG_EBSZ_VAL EBSZ_512
 397 # else
 398 #  error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_SIZE
 399 # endif
 400 # if CONFIG_MEM_ADD_WDTH == 8
 401 #  define CONFIG_EBCAW_VAL EBCAW_8
 402 # elif CONFIG_MEM_ADD_WDTH == 9
 403 #  define CONFIG_EBCAW_VAL EBCAW_9
 404 # elif CONFIG_MEM_ADD_WDTH == 10
 405 #  define CONFIG_EBCAW_VAL EBCAW_10
 406 # elif CONFIG_MEM_ADD_WDTH == 11
 407 #  define CONFIG_EBCAW_VAL EBCAW_11
 408 # else
 409 #  error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_ADD_WDTH
 410 # endif
 411 # define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE)
 412 #endif
 413 #endif
 414 #endif
 415
 416 /* Conflicting Column Address Widths Causes SDRAM Errors:
 417  * EB2CAW and EB3CAW must be the same
 418  */
 419 #if ANOMALY_05000362
 420 # if ((CONFIG_EBIU_SDBCTL_VAL & 0x30000000) >> 8) != (CONFIG_EBIU_SDBCTL_VAL & 0x00300000)
 421 #  error "Anomaly 05000362: EB2CAW and EB3CAW must be the same"
 422 # endif
 423 #endif
 424
 425 #endif /*  __ADSPBF60x__ */
 426
 427 __attribute__((always_inline)) static inline void
 428 program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
 429 {
 430         serial_putc('a');
 431
 432         /* Save the clock pieces that are used in baud rate calculation */
 433         if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
 434                 serial_putc('b');
 435 #ifdef __ADSPBF60x__
 436                 *sdivB = bfin_read_CGU_DIV();
 437                 *sdivB = ((*sdivB >> 8) & 0x1f) * ((*sdivB >> 5) & 0x7);
 438                 *vcoB = (bfin_read_CGU_CTL() >> 8) & 0x7f;
 439 #else
 440                 *sdivB = bfin_read_PLL_DIV() & 0xf;
 441                 *vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
 442 #endif
 443                 *divB = serial_early_get_div();
 444                 serial_putc('c');
 445         }
 446
 447         serial_putc('d');
 448
 449 #ifdef CONFIG_HW_WATCHDOG
 450 # ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
 451 #  define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
 452 # endif
 453         /* Program the watchdog with an initial timeout of ~20 seconds.
 454          * Hopefully that should be long enough to load the u-boot LDR
 455          * (from wherever) and then the common u-boot code can take over.
 456          * In bypass mode, the start.S would have already set a much lower
 457          * timeout, so don't clobber that.
 458          */
 459         if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
 460                 serial_putc('e');
 461 #ifdef __ADSPBF60x__
 462                 bfin_write_SEC_GCTL(0x2);
 463                 SSYNC();
 464                 bfin_write_SEC_FCTL(0xc1);
 465                 bfin_write_SEC_SCTL(2, bfin_read_SEC_SCTL(2) | 0x6);
 466
 467                 bfin_write_SEC_CCTL(0x2);
 468                 SSYNC();
 469                 bfin_write_SEC_GCTL(0x1);
 470                 bfin_write_SEC_CCTL(0x1);
 471 #endif
 472                 bfin_write_WDOG_CTL(WDDIS);
 473                 SSYNC();
 474                 bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
 475 #if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART
 476                 bfin_write_WDOG_CTL(WDEN);
 477 #endif
 478                 serial_putc('f');
 479         }
 480 #endif
 481
 482         serial_putc('g');
 483
 484         /* Blackfin bootroms use the SPI slow read opcode instead of the SPI
 485          * fast read, so we need to slow down the SPI clock a lot more during
 486          * boot.  Once we switch over to u-boot's SPI flash driver, we'll
 487          * increase the speed appropriately.
 488          */
 489 #ifdef SPI_BAUD
 490         if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
 491                 serial_putc('h');
 492                 if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4)
 493                         bs->dFlags |= BFLAG_FASTREAD;
 494                 bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
 495                 serial_putc('i');
 496         }
 497 #endif
 498
 499         serial_putc('j');
 500 }
 501
 502 __attribute__((always_inline)) static inline bool
 503 maybe_self_refresh(ADI_BOOT_DATA *bs)
 504 {
 505         serial_putc('a');
 506
 507         if (!CONFIG_MEM_SIZE)
 508                 return false;
 509
 510 #ifdef __ADSPBF60x__
 511         /* resume from hibernate, return false let ddr initialize */
 512         if ((bfin_read32(DPM0_STAT) & 0xF0) == 0x50) {
 513                 serial_putc('b');
 514                 return false;
 515         }
 516
 517 #else /* __ADSPBF60x__ */
 518
 519         /* If external memory is enabled, put it into self refresh first. */
 520 #if defined(EBIU_RSTCTL)
 521         if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
 522                 serial_putc('b');
 523                 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ);
 524                 return true;
 525         }
 526 #elif defined(EBIU_SDGCTL)
 527         if (bfin_read_EBIU_SDBCTL() & EBE) {
 528                 serial_putc('b');
 529                 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
 530                 return true;
 531         }
 532 #endif
 533
 534 #endif /* __ADSPBF60x__ */
 535         serial_putc('c');
 536
 537         return false;
 538 }
 539
 540 __attribute__((always_inline)) static inline u16
 541 program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
 542 {
 543         u16 vr_ctl;
 544
 545         serial_putc('a');
 546
 547 #ifdef __ADSPBF60x__
 548         if (bfin_read_DMC0_STAT() & MEMINITDONE) {
 549                 bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ);
 550                 SSYNC();
 551                 while (!(bfin_read_DMC0_STAT() & SRACK))
 552                         continue;
 553         }
 554
 555         /* Don't set the same value of MSEL and DF to CGU_CTL */
 556         if ((bfin_read_CGU_CTL() & (MSEL_MASK | DF_MASK))
 557                         != CONFIG_CGU_CTL_VAL) {
 558                 bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL);
 559                 bfin_write_CGU_CTL(CONFIG_CGU_CTL_VAL);
 560                 while ((bfin_read_CGU_STAT() & (CLKSALGN | PLLBP)) ||
 561                                 !(bfin_read_CGU_STAT() & PLLLK))
 562                         continue;
 563         }
 564
 565         bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL | UPDT);
 566         while (bfin_read_CGU_STAT() & CLKSALGN)
 567                 continue;
 568
 569         if (bfin_read_DMC0_STAT() & MEMINITDONE) {
 570                 bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ);
 571                 SSYNC();
 572                 while (bfin_read_DMC0_STAT() & SRACK)
 573                         continue;
 574         }
 575
 576 #else /* __ADSPBF60x__ */
 577
 578         vr_ctl = bfin_read_VR_CTL();
 579
 580         serial_putc('b');
 581
 582         /* If we're entering self refresh, make sure it has happened. */
 583         if (put_into_srfs)
 584 #if defined(EBIU_RSTCTL)
 585                 while (!(bfin_read_EBIU_RSTCTL() & SRACK))
 586                         continue;
 587 #elif defined(EBIU_SDGCTL)
 588                 while (!(bfin_read_EBIU_SDSTAT() & SDSRA))
 589                         continue;
 590 #else
 591                 ;
 592 #endif
 593
 594         serial_putc('c');
 595
 596         /* With newer bootroms, we use the helper function to set up
 597          * the memory controller.  Older bootroms lacks such helpers
 598          * so we do it ourselves.
 599          */
 600         if (!ANOMALY_05000386) {
 601                 serial_putc('d');
 602
 603                 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
 604                 ADI_SYSCTRL_VALUES memory_settings;
 605                 uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_LOCKCNT;
 606                 if (!ANOMALY_05000440)
 607                         actions |= SYSCTRL_PLLDIV;
 608                 if (CONFIG_HAS_VR) {
 609                         actions |= SYSCTRL_VRCTL;
 610                         if (CONFIG_VR_CTL_VAL & FREQ_MASK)
 611                                 actions |= SYSCTRL_INTVOLTAGE;
 612                         else
 613                                 actions |= SYSCTRL_EXTVOLTAGE;
 614                         memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
 615                 } else
 616                         actions |= SYSCTRL_EXTVOLTAGE;
 617                 memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
 618                 memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
 619                 memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
 620 #if ANOMALY_05000432
 621                 bfin_write_SIC_IWR1(0);
 622 #endif
 623                 serial_putc('e');
 624                 bfrom_SysControl(actions, &memory_settings, NULL);
 625                 serial_putc('f');
 626                 if (ANOMALY_05000440)
 627                         bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
 628 #if ANOMALY_05000432
 629                 bfin_write_SIC_IWR1(-1);
 630 #endif
 631 #if ANOMALY_05000171
 632                 bfin_write_SICA_IWR0(-1);
 633                 bfin_write_SICA_IWR1(-1);
 634 #endif
 635                 serial_putc('g');
 636         } else {
 637                 serial_putc('h');
 638
 639                 /* Disable all peripheral wakeups except for the PLL event. */
 640 #ifdef SIC_IWR0
 641                 bfin_write_SIC_IWR0(1);
 642                 bfin_write_SIC_IWR1(0);
 643 # ifdef SIC_IWR2
 644                 bfin_write_SIC_IWR2(0);
 645 # endif
 646 #elif defined(SICA_IWR0)
 647                 bfin_write_SICA_IWR0(1);
 648                 bfin_write_SICA_IWR1(0);
 649 #elif defined(SIC_IWR)
 650                 bfin_write_SIC_IWR(1);
 651 #endif
 652
 653                 serial_putc('i');
 654
 655                 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
 656                 bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
 657
 658                 serial_putc('j');
 659
 660                 /* Only reprogram when needed to avoid triggering unnecessary
 661                  * PLL relock sequences.
 662                  */
 663                 if (vr_ctl != CONFIG_VR_CTL_VAL) {
 664                         serial_putc('?');
 665                         bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
 666                         asm("idle;");
 667                         serial_putc('!');
 668                 }
 669
 670                 serial_putc('k');
 671
 672                 bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
 673
 674                 serial_putc('l');
 675
 676                 /* Only reprogram when needed to avoid triggering unnecessary
 677                  * PLL relock sequences.
 678                  */
 679                 if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
 680                         serial_putc('?');
 681                         bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
 682                         asm("idle;");
 683                         serial_putc('!');
 684                 }
 685
 686                 serial_putc('m');
 687
 688                 /* Restore all peripheral wakeups. */
 689 #ifdef SIC_IWR0
 690                 bfin_write_SIC_IWR0(-1);
 691                 bfin_write_SIC_IWR1(-1);
 692 # ifdef SIC_IWR2
 693                 bfin_write_SIC_IWR2(-1);
 694 # endif
 695 #elif defined(SICA_IWR0)
 696                 bfin_write_SICA_IWR0(-1);
 697                 bfin_write_SICA_IWR1(-1);
 698 #elif defined(SIC_IWR)
 699                 bfin_write_SIC_IWR(-1);
 700 #endif
 701
 702                 serial_putc('n');
 703         }
 704
 705 #endif /* __ADSPBF60x__ */
 706
 707         serial_putc('o');
 708
 709         return vr_ctl;
 710 }
 711
 712 __attribute__((always_inline)) static inline void
 713 update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
 714 {
 715         /* Since we've changed the SCLK above, we may need to update
 716          * the UART divisors (UART baud rates are based on SCLK).
 717          * Do the division by hand as there are no native instructions
 718          * for dividing which means we'd generate a libgcc reference.
 719          */
 720         unsigned int sdivR, vcoR;
 721         unsigned int dividend;
 722         unsigned int divisor;
 723         unsigned int quotient;
 724
 725         serial_putc('a');
 726
 727 #ifdef __ADSPBF60x__
 728         sdivR = bfin_read_CGU_DIV();
 729         sdivR = ((sdivR >> 8) & 0x1f) * ((sdivR >> 5) & 0x7);
 730         vcoR = (bfin_read_CGU_CTL() >> 8) & 0x7f;
 731 #else
 732         sdivR = bfin_read_PLL_DIV() & 0xf;
 733         vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
 734 #endif
 735
 736         dividend = sdivB * divB * vcoR;
 737         divisor = vcoB * sdivR;
 738         quotient = early_division(dividend, divisor);
 739         serial_early_put_div(quotient - ANOMALY_05000230);
 740         serial_putc('c');
 741 }
 742
 743 __attribute__((always_inline)) static inline void
 744 program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
 745 {
 746         serial_putc('a');
 747
 748         if (!CONFIG_MEM_SIZE)
 749                 return;
 750
 751         serial_putc('b');
 752
 753 #ifdef __ADSPBF60x__
 754         int dlldatacycle;
 755         int dll_ctl;
 756         int i = 0;
 757
 758         if (CONFIG_BFIN_GET_DCLK_M ==  125)
 759                 i = 0;
 760         else if (CONFIG_BFIN_GET_DCLK_M ==  133)
 761                 i = 1;
 762         else if (CONFIG_BFIN_GET_DCLK_M ==  150)
 763                 i = 2;
 764         else if (CONFIG_BFIN_GET_DCLK_M ==  166)
 765                 i = 3;
 766         else if (CONFIG_BFIN_GET_DCLK_M ==  200)
 767                 i = 4;
 768         else if (CONFIG_BFIN_GET_DCLK_M ==  225)
 769                 i = 5;
 770         else if (CONFIG_BFIN_GET_DCLK_M ==  250)
 771                 i = 6;
 772
 773 #if 0
 774         for (i = 0; i < ARRAY_SIZE(ddr_config_table); i++)
 775                 if (CONFIG_BFIN_GET_DCLK_M == ddr_config_table[i].ddr_clk)
 776                         break;
 777 #endif
 778
 779 #ifndef CONFIG_DMC_DDRCFG
 780         bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg);
 781 #else
 782         bfin_write_DMC0_CFG(CONFIG_DMC_DDRCFG);
 783 #endif
 784 #ifndef CONFIG_DMC_DDRTR0
 785         bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0);
 786 #else
 787         bfin_write_DMC0_TR0(CONFIG_DMC_DDRTR0);
 788 #endif
 789 #ifndef CONFIG_DMC_DDRTR1
 790         bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1);
 791 #else
 792         bfin_write_DMC0_TR1(CONFIG_DMC_DDRTR1);
 793 #endif
 794 #ifndef CONFIG_DMC_DDRTR2
 795         bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2);
 796 #else
 797         bfin_write_DMC0_TR2(CONFIG_DMC_DDRTR2);
 798 #endif
 799 #ifndef CONFIG_DMC_DDRMR
 800         bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr);
 801 #else
 802         bfin_write_DMC0_MR(CONFIG_DMC_DDRMR);
 803 #endif
 804 #ifndef CONFIG_DMC_DDREMR1
 805         bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1);
 806 #else
 807         bfin_write_DMC0_EMR1(CONFIG_DMC_DDREMR1);
 808 #endif
 809 #ifndef CONFIG_DMC_DDRCTL
 810         bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl);
 811 #else
 812         bfin_write_DMC0_CTL(CONFIG_DMC_DDRCTL);
 813 #endif
 814
 815         SSYNC();
 816         while (!(bfin_read_DMC0_STAT() & MEMINITDONE))
 817                 continue;
 818
 819         dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >>
 820                         PHYRDPHASE_OFFSET;
 821         dll_ctl = bfin_read_DMC0_DLLCTL();
 822         dll_ctl &= 0x0ff;
 823         bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET));
 824
 825         SSYNC();
 826         while (!(bfin_read_DMC0_STAT() & DLLCALDONE))
 827                 continue;
 828         serial_putc('!');
 829
 830 #else /* __ADSPBF60x__ */
 831
 832         /* Program the external memory controller before we come out of
 833          * self-refresh.  This only works with our SDRAM controller.
 834          */
 835 #ifdef EBIU_SDGCTL
 836 # ifdef CONFIG_EBIU_SDRRC_VAL
 837         bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
 838 # endif
 839 # ifdef CONFIG_EBIU_SDBCTL_VAL
 840         bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
 841 # endif
 842 # ifdef CONFIG_EBIU_SDGCTL_VAL
 843         bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
 844 # endif
 845 #endif
 846
 847         serial_putc('c');
 848
 849         /* Now that we've reprogrammed, take things out of self refresh. */
 850         if (put_into_srfs)
 851 #if defined(EBIU_RSTCTL)
 852                 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
 853 #elif defined(EBIU_SDGCTL)
 854                 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS));
 855 #endif
 856
 857         serial_putc('d');
 858
 859         /* Our DDR controller sucks and cannot be programmed while in
 860          * self-refresh.  So we have to pull it out before programming.
 861          */
 862 #ifdef EBIU_RSTCTL
 863 # ifdef CONFIG_EBIU_RSTCTL_VAL
 864         bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
 865 # endif
 866 # ifdef CONFIG_EBIU_DDRCTL0_VAL
 867         bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
 868 # endif
 869 # ifdef CONFIG_EBIU_DDRCTL1_VAL
 870         bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
 871 # endif
 872 # ifdef CONFIG_EBIU_DDRCTL2_VAL
 873         bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
 874 # endif
 875 # ifdef CONFIG_EBIU_DDRCTL3_VAL
 876         /* default is disable, so don't need to force this */
 877         bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
 878 # endif
 879 # ifdef CONFIG_EBIU_DDRQUE_VAL
 880         bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | CONFIG_EBIU_DDRQUE_VAL);
 881 # endif
 882 #endif
 883
 884 #endif /* __ADSPBF60x__ */
 885         serial_putc('e');
 886 }
 887
 888 __attribute__((always_inline)) static inline void
 889 check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs)
 890 {
 891         serial_putc('a');
 892
 893         if (!CONFIG_MEM_SIZE)
 894                 return;
 895
 896         serial_putc('b');
 897 #ifdef __ADSPBF60x__
 898         if (bfin_read32(DPM0_RESTORE0) != 0) {
 899                 uint32_t reg = bfin_read_DMC0_CTL();
 900                 reg &= ~0x8;
 901                 bfin_write_DMC0_CTL(reg);
 902
 903                 while ((bfin_read_DMC0_STAT() & 0x8))
 904                         continue;
 905                 while (!(bfin_read_DMC0_STAT() & 0x1))
 906                         continue;
 907
 908                 serial_putc('z');
 909                 uint32_t *hibernate_magic = bfin_read32(DPM0_RESTORE4);
 910                 SSYNC(); /* make sure memory controller is done */
 911                 if (hibernate_magic[0] == 0xDEADBEEF) {
 912                         serial_putc('c');
 913                         SSYNC();
 914                         bfin_write_EVT15(hibernate_magic[1]);
 915                         bfin_write_IMASK(EVT_IVG15);
 916                         __asm__ __volatile__ (
 917                                 /* load reti early to avoid anomaly 281 */
 918                                 "reti = %2;"
 919                                 /* clear hibernate magic */
 920                                 "[%0] = %1;"
 921                                 /* load stack pointer */
 922                                 "SP = [%0 + 8];"
 923                                 /* lower ourselves from reset ivg to ivg15 */
 924                                 "raise 15;"
 925                                 "nop;nop;nop;"
 926                                 "rti;"
 927                                 :
 928                                 : "p"(hibernate_magic),
 929                                 "d"(0x2000 /* jump.s 0 */),
 930                                 "d"(0xffa00000)
 931                         );
 932                 }
 933
 934
 935         }
 936 #else
 937         /* Are we coming out of hibernate (suspend to memory) ?
 938          * The memory layout is:
 939          * 0x0: hibernate magic for anomaly 307 (0xDEADBEEF)
 940          * 0x4: return address
 941          * 0x8: stack pointer
 942          *
 943          * SCKELOW is unreliable on older parts (anomaly 307)
 944          */
 945         if (ANOMALY_05000307 || vr_ctl & 0x8000) {
 946                 uint32_t *hibernate_magic = 0;
 947
 948                 SSYNC();
 949                 if (hibernate_magic[0] == 0xDEADBEEF) {
 950                         serial_putc('c');
 951                         bfin_write_EVT15(hibernate_magic[1]);
 952                         bfin_write_IMASK(EVT_IVG15);
 953                         __asm__ __volatile__ (
 954                                 /* load reti early to avoid anomaly 281 */
 955                                 "reti = %0;"
 956                                 /* clear hibernate magic */
 957                                 "[%0] = %1;"
 958                                 /* load stack pointer */
 959                                 "SP = [%0 + 8];"
 960                                 /* lower ourselves from reset ivg to ivg15 */
 961                                 "raise 15;"
 962                                 "rti;"
 963                                 :
 964                                 : "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */)
 965                         );
 966                 }
 967                 serial_putc('d');
 968         }
 969 #endif
 970
 971         serial_putc('e');
 972 }
 973
 974 BOOTROM_CALLED_FUNC_ATTR
 975 void initcode(ADI_BOOT_DATA *bs)
 976 {
 977         ADI_BOOT_DATA bootstruct_scratch;
 978
 979         /* Setup NMI handler before anything else */
 980         program_nmi_handler();
 981
 982         serial_init();
 983
 984         serial_putc('A');
 985
 986         /* If the bootstruct is NULL, then it's because we're loading
 987          * dynamically and not via LDR (bootrom).  So set the struct to
 988          * some scratch space.
 989          */
 990         if (!bs)
 991                 bs = &bootstruct_scratch;
 992
 993         serial_putc('B');
 994         bool put_into_srfs = maybe_self_refresh(bs);
 995
 996         serial_putc('C');
 997         uint sdivB, divB, vcoB;
 998         program_early_devices(bs, &sdivB, &divB, &vcoB);
 999
1000         serial_putc('D');
1001         u16 vr_ctl = program_clocks(bs, put_into_srfs);
1002
1003         serial_putc('E');
1004         update_serial_clocks(bs, sdivB, divB, vcoB);
1005
1006         serial_putc('F');
1007         program_memory_controller(bs, put_into_srfs);
1008
1009         serial_putc('G');
1010         check_hibernation(bs, vr_ctl, put_into_srfs);
1011
1012         serial_putc('H');
1013         program_async_controller(bs);
1014
1015 #ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
1016         serial_putc('I');
1017         /* Tell the bootrom where our entry point is so that it knows
1018          * where to jump to when finishing processing the LDR.  This
1019          * allows us to avoid small jump blocks in the LDR, and also
1020          * works around anomaly 05000389 (init address in external
1021          * memory causes bootrom to trigger external addressing IVHW).
1022          */
1023         if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
1024                 bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE);
1025 #endif
1026
1027         serial_putc('>');
1028         serial_putc('\n');
1029
1030         serial_deinit();
1031 }