2 * interrupt.S - trampoline default exceptions/interrupts to C handlers
4 * Copyright (c) 2005-2009 Analog Devices Inc.
5 * Licensed under the GPL-2 or later.
9 #include <asm/blackfin.h>
10 #include <asm/entry.h>
11 #include <asm/ptrace.h>
12 #include <asm/deferred.h>
13 #include <asm/mach-common/bits/core.h>
17 /* default entry point for exceptions */
19 CONFIG_BFIN_SCRATCH_REG = sp;
20 sp.l = LO(L1_SRAM_SCRATCH_END - 20);
21 sp.h = HI(L1_SRAM_SCRATCH_END - 20);
24 r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
25 r1 = 3; /* EVT3 space */
30 #ifdef CONFIG_EXCEPTION_DEFER
32 IF CC JUMP .Lexit_trap;
34 /* To avoid double faults, lower our priority to IRQ5 */
35 p4.l = lo(COREMMR_BASE);
36 p4.h = hi(COREMMR_BASE);
38 r7.h = _exception_to_level5;
39 r7.l = _exception_to_level5;
40 [p4 + (EVT5 - COREMMR_BASE)] = r7;
43 * Save these registers, as they are only valid in exception context
44 * (where we are now - as soon as we defer to IRQ5, they can change)
46 p5.l = _deferred_regs;
47 p5.h = _deferred_regs;
48 r6 = [p4 + (DCPLB_FAULT_ADDR - COREMMR_BASE)];
49 [p5 + (deferred_regs_DCPLB_FAULT_ADDR * 4)] = r6;
51 r6 = [p4 + (ICPLB_FAULT_ADDR - COREMMR_BASE)];
52 [p5 + (deferred_regs_ICPLB_FAULT_ADDR * 4)] = r6;
54 /* Save the state of single stepping */
56 [p5 + (deferred_regs_SYSCFG * 4)] = r6;
57 /* Clear it while we handle the exception in IRQ5 mode
58 * RESTORE_ALL_SYS will load it, so all we need to do is store it
61 BITCLR(r6, SYSCFG_SSSTEP_P);
62 [SP + PT_SYSCFG] = r6;
64 /* Since we are going to clobber RETX, we need to save it */
66 [p5 + (deferred_regs_retx * 4)] = r6;
68 /* Save the current IMASK, since we change in order to jump to level 5 */
70 [p5 + (deferred_regs_IMASK * 4)] = r6;
72 /* Disable all interrupts, but make sure level 5 is enabled so
73 * we can switch to that level.
78 /* Clobber RETX so we don't end up back at a faulting instruction */
81 /* In case interrupts are disabled IPEND[4] (global interrupt disable bit)
82 * clear it (re-enabling interrupts again) by the special sequence of pushing
83 * RETI onto the stack. This way we can lower ourselves to IVG5 even if the
84 * exception was taken after the interrupt handler was called but before it
85 * got a chance to enable global interrupts itself.
102 sp = CONFIG_BFIN_SCRATCH_REG;
106 #ifdef CONFIG_EXCEPTION_DEFER
107 /* Deferred (IRQ5) exceptions */
108 ENTRY(_exception_to_level5)
111 /* Now we have to fix things up */
119 p4.l = _deferred_regs;
120 p4.h = _deferred_regs;
121 r0 = [p4 + (deferred_regs_retx * 4)];
124 r0 = [p4 + (deferred_regs_SYSCFG * 4)];
125 [sp + PT_SYSCFG] = r0;
127 r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
128 r1 = 5; /* EVT5 space */
134 r0 = [p4 + (deferred_regs_IMASK * 4)];
140 ENDPROC(_exception_to_level5)
143 /* default entry point for interrupts */
146 r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
152 ENDPROC(_evt_default)