2 * reset.c - logic for resetting the cpu
4 * Copyright (c) 2005-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
11 #include <asm/blackfin.h>
12 #include <asm/mach-common/bits/bootrom.h>
15 /* A system soft reset makes external memory unusable so force
16 * this function into L1. We use the compiler ssync here rather
17 * than SSYNC() because it's safe (no interrupts and such) and
18 * we save some L1. We do not need to force sanity in the SYSCR
19 * register as the BMODE selection bit is cleared by the soft
20 * reset while the Core B bit (on dual core parts) is cleared by
23 __attribute__ ((__l1_text__, __noreturn__))
24 static void bfin_reset(void)
26 /* Wait for completion of "system" events such as cache line
27 * line fills so that we avoid infinite stalls later on as
28 * much as possible. This code is in L1, so it won't trigger
29 * any such event after this point in time.
31 __builtin_bfin_ssync();
33 /* Initiate System software reset. */
34 bfin_write_SWRST(0x7);
36 /* Due to the way reset is handled in the hardware, we need
37 * to delay for 10 SCLKS. The only reliable way to do this is
38 * to calculate the CCLK/SCLK ratio and multiply 10. For now,
39 * we'll assume worse case which is a 1:15 ratio.
42 "LSETUP (1f, 1f) LC0 = %0\n"
49 /* Clear System software reset */
52 /* The BF526 ROM will crash during reset */
53 #if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
54 /* Seems to be fixed with newer parts though ... */
55 if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
59 /* Wait for the SWRST write to complete. Cannot rely on SSYNC
60 * though as the System state is all reset now.
63 "LSETUP (1f, 1f) LC1 = %0\n"
71 /* Issue core reset */
75 /* We need to trampoline ourselves up into L1 since our linker
76 * does not have relaxtion support and will only generate a
77 * PC relative call with a 25 bit immediate. This is not enough
78 * to get us from the top of SDRAM into L1.
80 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
84 if (ANOMALY_05000353 || ANOMALY_05000386)
86 asm("jump (%0);" : : "a" (bfin_reset));
88 bfrom_SoftReset((void *)(L1_SRAM_SCRATCH_END - 20));