2 * U-boot - start.S Startup file for Blackfin u-boot
4 * Copyright (c) 2005-2008 Analog Devices Inc.
6 * This file is based on head.S
7 * Copyright (c) 2003 Metrowerks/Motorola
8 * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
9 * Kenneth Albanowski <kjahds@kjahds.com>,
10 * The Silver Hammer Group, Ltd.
11 * (c) 1995, Dionne & Associates
12 * (c) 1995, DKG Display Tech.
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
34 #include <asm/blackfin.h>
35 #include <asm/mach-common/bits/core.h>
36 #include <asm/mach-common/bits/pll.h>
40 /* It may seem odd that we make calls to functions even though we haven't
41 * relocated ourselves yet out of {flash,ram,wherever}. This is OK because
42 * the "call" instruction in the Blackfin architecture is actually PC
43 * relative. So we can call functions all we want and not worry about them
44 * not being relocated yet.
50 /* Set our initial stack to L1 scratch space */
51 sp.l = LO(L1_SRAM_SCRATCH_END - 20);
52 sp.h = HI(L1_SRAM_SCRATCH_END - 20);
54 /* Optimization register tricks: keep a base value in the
55 * reserved P registers so we use the load/store with an
56 * offset syntax. R0 = [P5 + <constant>];
57 * P4 - system MMR base
60 #ifdef CONFIG_HW_WATCHDOG
62 p4.h = HI(SYSMMR_BASE);
65 p5.h = HI(COREMMR_BASE);
67 #ifdef CONFIG_HW_WATCHDOG
69 # ifndef CONFIG_HW_WATCHDOG_TIMEOUT_START
70 # define CONFIG_HW_WATCHDOG_TIMEOUT_START 5000
72 /* Program the watchdog with an initial timeout of ~5 seconds.
73 * That should be long enough to bootstrap ourselves up and
74 * then the common u-boot code can take over.
77 r0.h = HI(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_START));
78 [p4 + (WDOG_CNT - SYSMMR_BASE)] = r0;
79 /* fire up the watchdog - R0.L above needs to be 0x0000 */
80 W[p4 + (WDOG_CTL - SYSMMR_BASE)] = r0;
84 /* Turn on the serial for debugging the init process */
88 serial_early_puts("Init Registers");
90 /* Disable self-nested interrupts and enable CYCLES for udelay() */
94 /* Zero out registers required by Blackfin ABI.
95 * http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface
98 /* Disable circular buffers */
103 /* Disable hardware loops in case we were started by 'go' */
107 /* Save RETX so we can pass it while booting Linux */
111 /* Figure out where we are currently executing so that we can decide
112 * how to best reprogram and relocate things. We'll pass below:
113 * R4: load address of _start
114 * R5: current (not load) address of _start
116 serial_early_puts("Find ourselves");
127 /* Inform upper layers if we had to do the relocation ourselves.
128 * This allows us to detect whether we were loaded by 'go 0x1000'
129 * or by the bootrom from an LDR. "R6" is "loaded_from_ldr".
133 if cc jump .Lnorelocate;
136 /* Turn off caches as they require CPLBs and a CPLB miss requires
137 * a software exception handler to process it. But we're about to
138 * clobber any previous executing software (like U-Boot that just
139 * launched a new U-Boot via 'go'), so any handler state will be
140 * unreliable after the memcpy below.
142 serial_early_puts("Kill Caches");
144 [p5 + (IMEM_CONTROL - COREMMR_BASE)] = r0;
145 [p5 + (DMEM_CONTROL - COREMMR_BASE)] = r0;
148 /* In bypass mode, we don't have an LDR with an init block
149 * so we need to explicitly call it ourselves. This will
150 * reprogram our clocks, memory, and setup our async banks.
152 serial_early_puts("Program Clocks");
154 /* if we're executing >=0x20000000, then we dont need to dma */
158 if cc jump .Ldma_and_reprogram;
160 r6 = 1 (x); /* fake loaded_from_ldr = 1 */
162 r0 = 0 (x); /* set bootstruct to NULL */
166 /* we're sitting in external memory, so dma into L1 and reprogram */
168 r0.l = LO(L1_INST_SRAM);
169 r0.h = HI(L1_INST_SRAM);
170 r1.l = __initcode_lma;
171 r1.h = __initcode_lma;
172 r2.l = __initcode_len;
173 r2.h = __initcode_len;
174 r1 = r1 - r4; /* convert r1 from load address of initcode ... */
175 r1 = r1 + r5; /* ... to current (not load) address of initcode */
177 call _dma_memcpy_nocache;
178 r0 = 0 (x); /* set bootstruct to NULL */
181 /* Since we reprogrammed SCLK, we need to update the serial divisor */
183 serial_early_set_baud
186 /* Relocate from wherever we are (FLASH/RAM/etc...) to the hardcoded
187 * monitor location in the end of RAM. We know that memcpy() only
188 * uses registers, so it is safe to call here. Note that this only
189 * copies to external memory ... we do not start executing out of
190 * it yet (see "lower to 15" below).
192 serial_early_puts("Relocate");
195 r2.l = LO(CONFIG_SYS_MONITOR_LEN);
196 r2.h = HI(CONFIG_SYS_MONITOR_LEN);
200 /* Initialize BSS section ... we know that memset() does not
201 * use the BSS, so it is safe to call here. The bootrom LDR
202 * takes care of clearing things for us.
204 serial_early_puts("Zero BSS");
214 /* Setup the actual stack in external memory */
215 sp.h = HI(CONFIG_STACKBASE);
216 sp.l = LO(CONFIG_STACKBASE);
219 /* Now lower ourselves from the highest interrupt level to
220 * the lowest. We do this by masking all interrupts but 15,
221 * setting the 15 handler to ".Lenable_nested", raising the 15
222 * interrupt, and then returning from the highest interrupt
223 * level to the dummy "jump" until the interrupt controller
224 * services the pending 15 interrupt. If executing out of
225 * flash, these steps also changes the code flow from flash
226 * to external memory.
228 serial_early_puts("Lower to 15");
231 p1.l = .Lenable_nested;
232 p1.h = .Lenable_nested;
233 [p5 + (EVT15 - COREMMR_BASE)] = p1;
242 /* Enable nested interrupts before continuing with cpu init */