3 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 /*------------------------------------------------------------------------------+ */
29 * This source code is dual-licensed. You may use it under the terms of the
30 * GNU General Public License version 2, or under the license below.
32 * This source code has been made available to you by IBM on an AS-IS
33 * basis. Anyone receiving this source is licensed under IBM
34 * copyrights to use it in any way he or she deems fit, including
35 * copying it, modifying it, compiling it, and redistributing it either
36 * with or without modifications. No license under IBM patents or
37 * patent applications is to be implied by the copyright license.
39 * Any user of this software should understand that IBM cannot provide
40 * technical support for this software and will not be responsible for
41 * any consequences resulting from the use of this software.
43 * Any person who transfers this source code or any derivative work
44 * must include the IBM copyright notice, this paragraph, and the
45 * preceding two paragraphs in the transferred software.
47 * COPYRIGHT I B M CORPORATION 1995
48 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
50 /*------------------------------------------------------------------------------- */
55 #include <asm/ibmpc.h>
57 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
61 DECLARE_GLOBAL_DATA_PTR;
76 /*-----------------------------------------------------------------------------+
77 | Line Status Register.
78 +-----------------------------------------------------------------------------*/
79 #define asyncLSRDataReady1 0x01
80 #define asyncLSROverrunError1 0x02
81 #define asyncLSRParityError1 0x04
82 #define asyncLSRFramingError1 0x08
83 #define asyncLSRBreakInterrupt1 0x10
84 #define asyncLSRTxHoldEmpty1 0x20
85 #define asyncLSRTxShiftEmpty1 0x40
86 #define asyncLSRRxFifoError1 0x80
89 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
90 /*-----------------------------------------------------------------------------+
92 +-----------------------------------------------------------------------------*/
100 volatile serial_buffer_t buf_info;
101 static int serial_buffer_active=0;
105 static int serial_div(int baudrate)
128 * Minimal serial functions needed to use one of the SMC ports
129 * as serial console interface.
132 int serial_init(void)
135 int bdiv = serial_div(gd->baudrate);
137 outb(0x80, UART0_BASE + UART_LCR); /* set DLAB bit */
138 outb(bdiv, UART0_BASE + UART_DLL); /* set baudrate divisor */
139 outb(bdiv >> 8, UART0_BASE + UART_DLM);/* set baudrate divisor */
140 outb(0x03, UART0_BASE + UART_LCR); /* clear DLAB; set 8 bits, no parity */
141 outb(0x01, UART0_BASE + UART_FCR); /* enable FIFO */
142 outb(0x0b, UART0_BASE + UART_MCR); /* Set DTR and RTS active */
143 val = inb(UART0_BASE + UART_LSR); /* clear line status */
144 val = inb(UART0_BASE + UART_RBR); /* read receive buffer */
145 outb(0x00, UART0_BASE + UART_SCR); /* set scratchpad */
146 outb(0x00, UART0_BASE + UART_IER); /* set interrupt enable reg */
152 void serial_setbrg(void)
156 bdiv = serial_div(gd->baudrate);
158 outb(0x80, UART0_BASE + UART_LCR); /* set DLAB bit */
159 outb(bdiv&0xff, UART0_BASE + UART_DLL); /* set baudrate divisor */
160 outb(bdiv >> 8, UART0_BASE + UART_DLM);/* set baudrate divisor */
161 outb(0x03, UART0_BASE + UART_LCR); /* clear DLAB; set 8 bits, no parity */
165 void serial_putc(const char c)
172 /* check THRE bit, wait for transmiter available */
173 for (i = 1; i < 3500; i++) {
174 if ((inb (UART0_BASE + UART_LSR) & 0x20) == 0x20) {
179 outb(c, UART0_BASE + UART_THR); /* put character out */
183 void serial_puts(const char *s)
191 int serial_getc(void)
193 unsigned char status = 0;
195 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
196 if (serial_buffer_active) {
197 return serial_buffered_getc();
202 #if defined(CONFIG_HW_WATCHDOG)
203 WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */
204 #endif /* CONFIG_HW_WATCHDOG */
205 status = inb(UART0_BASE + UART_LSR);
206 if ((status & asyncLSRDataReady1) != 0x0) {
209 if ((status & ( asyncLSRFramingError1 |
210 asyncLSROverrunError1 |
211 asyncLSRParityError1 |
212 asyncLSRBreakInterrupt1 )) != 0) {
213 outb(asyncLSRFramingError1 |
214 asyncLSROverrunError1 |
215 asyncLSRParityError1 |
216 asyncLSRBreakInterrupt1, UART0_BASE + UART_LSR);
219 return (0x000000ff & (int) inb (UART0_BASE));
223 int serial_tstc(void)
225 unsigned char status;
227 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
228 if (serial_buffer_active) {
229 return serial_buffered_tstc();
233 status = inb(UART0_BASE + UART_LSR);
234 if ((status & asyncLSRDataReady1) != 0x0) {
237 if ((status & ( asyncLSRFramingError1 |
238 asyncLSROverrunError1 |
239 asyncLSRParityError1 |
240 asyncLSRBreakInterrupt1 )) != 0) {
241 outb(asyncLSRFramingError1 |
242 asyncLSROverrunError1 |
243 asyncLSRParityError1 |
244 asyncLSRBreakInterrupt1, UART0_BASE + UART_LSR);
250 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
252 void serial_isr(void *arg)
256 int rx_put = buf_info.rx_put;
258 if (buf_info.rx_get <= rx_put) {
259 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - buf_info.rx_get);
261 space = buf_info.rx_get - rx_put;
264 while (inb(UART0_BASE + UART_LSR) & 1) {
267 buf_info.rx_buffer[rx_put++] = c;
270 if (rx_put == buf_info.rx_get) {
272 if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) {
277 if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) {
279 if (0 == buf_info.rx_get) {
286 if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
287 /* Stop flow by setting RTS inactive */
288 outb(inb(UART0_BASE + UART_MCR) & (0xFF ^ 0x02),
289 UART0_BASE + UART_MCR);
292 buf_info.rx_put = rx_put;
295 void serial_buffered_init(void)
297 serial_puts ("Switching to interrupt driven serial input mode.\n");
298 buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
302 if (inb (UART0_BASE + UART_MSR) & 0x10) {
303 serial_puts ("Check CTS signal present on serial port: OK.\n");
306 serial_puts ("WARNING: CTS signal not present on serial port.\n");
310 irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
311 serial_isr /*interrupt_handler_t *handler */ ,
312 (void *) &buf_info /*void *arg */ );
314 /* Enable "RX Data Available" Interrupt on UART */
315 /* outb(inb(UART0_BASE + UART_IER) |0x01, UART0_BASE + UART_IER); */
316 outb(0x01, UART0_BASE + UART_IER);
318 /* Set DTR and RTS active, enable interrupts */
319 outb(inb (UART0_BASE + UART_MCR) | 0x0b, UART0_BASE + UART_MCR);
321 /* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */
322 outb( /*(1 << 6) |*/ 1, UART0_BASE + UART_FCR);
324 serial_buffer_active = 1;
327 void serial_buffered_putc (const char c)
331 #if defined(CONFIG_HW_WATCHDOG)
332 while (!(inb (UART0_BASE + UART_MSR) & 0x10))
336 for (i=0;i<1000;i++) {
337 if ((inb (UART0_BASE + UART_MSR) & 0x10)) {
345 if ((inb (UART0_BASE + UART_MSR) & 0x10)) {
354 void serial_buffered_puts(const char *s)
359 int serial_buffered_getc(void)
363 int rx_get = buf_info.rx_get;
366 #if defined(CONFIG_HW_WATCHDOG)
367 while (rx_get == buf_info.rx_put)
370 while (rx_get == buf_info.rx_put);
372 c = buf_info.rx_buffer[rx_get++];
373 if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO) {
376 buf_info.rx_get = rx_get;
378 rx_put = buf_info.rx_put;
379 if (rx_get <= rx_put) {
380 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
382 space = rx_get - rx_put;
384 if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
385 /* Start flow by setting RTS active */
386 outb(inb (UART0_BASE + UART_MCR) | 0x02, UART0_BASE + UART_MCR);
392 int serial_buffered_tstc(void)
394 return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
397 #endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
400 #if defined(CONFIG_CMD_KGDB)
402 AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
404 - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
405 configuration has been already done
406 - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
407 configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
409 #if (CONFIG_KGDB_SER_INDEX & 2)
410 void kgdb_serial_init(void)
413 bdiv = serial_div (CONFIG_KGDB_BAUDRATE);
416 * Init onboard 16550 UART
418 outb(0x80, UART1_BASE + UART_LCR); /* set DLAB bit */
419 outb((bdiv & 0xff), UART1_BASE + UART_DLL); /* set divisor for 9600 baud */
420 outb((bdiv >> 8 ), UART1_BASE + UART_DLM); /* set divisor for 9600 baud */
421 outb(0x03, UART1_BASE + UART_LCR); /* line control 8 bits no parity */
422 outb(0x00, UART1_BASE + UART_FCR); /* disable FIFO */
423 outb(0x00, UART1_BASE + UART_MCR); /* no modem control DTR RTS */
424 val = inb(UART1_BASE + UART_LSR); /* clear line status */
425 val = inb(UART1_BASE + UART_RBR); /* read receive buffer */
426 outb(0x00, UART1_BASE + UART_SCR); /* set scratchpad */
427 outb(0x00, UART1_BASE + UART_IER); /* set interrupt enable reg */
431 void putDebugChar(const char c)
436 outb(c, UART1_BASE + UART_THR); /* put character out */
438 /* check THRE bit, wait for transfer done */
439 while ((inb(UART1_BASE + UART_LSR) & 0x20) != 0x20);
443 void putDebugStr(const char *s)
451 int getDebugChar(void)
453 unsigned char status = 0;
456 status = inb(UART1_BASE + UART_LSR);
457 if ((status & asyncLSRDataReady1) != 0x0) {
460 if ((status & ( asyncLSRFramingError1 |
461 asyncLSROverrunError1 |
462 asyncLSRParityError1 |
463 asyncLSRBreakInterrupt1 )) != 0) {
464 outb(asyncLSRFramingError1 |
465 asyncLSROverrunError1 |
466 asyncLSRParityError1 |
467 asyncLSRBreakInterrupt1, UART1_BASE + UART_LSR);
470 return (0x000000ff & (int) inb(UART1_BASE));
474 void kgdb_interruptible(int yes)
479 #else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
481 void kgdb_serial_init(void)
483 serial_printf ("[on serial] ");
486 void putDebugChar(int c)
491 void putDebugStr(const char *str)
496 int getDebugChar(void)
498 return serial_getc ();
501 void kgdb_interruptible(int yes)
505 #endif /* (CONFIG_KGDB_SER_INDEX & 2) */